Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2002-01-22
2004-03-09
Nghiem, Michael (Department: 2863)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C365S201000, C377S020000, C702S123000
Reexamination Certificate
active
06704676
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the integrated circuit technology field. More specifically, the invention relates to a method for identifying an operating property of an integrated circuit, wherein, in at least one test sequence, the operating property is ascertained and then output. The invention also pertains to a corresponding circuit configuration.
Integrated circuits are tested for functionality after fabrication. To that end, the integrated circuit is connected to an automatic test machine and changed over to a test mode. The automatic test machine operates the circuit with different input stimuli under a wide variety of operating conditions and compares the result calculated by the circuit in the test mode with a predetermined reference value. The circuit can thereby be operated with the application of supply voltages of different magnitudes, different temperatures and/or different clock frequencies.
A characteristic operating property of an integrated semiconductor memory, in particular of an SDRAM (Synchronous Dynamic Random Access Memory), is the operating speed of the memory. SDRAMs which are offered for different speed classes usually comprise the same circuit. The dictates of fabrication give rise to variations in the quality of the circuit, so that one portion of the chips operates reliably at a higher speed and another portion of the chips operates reliably only at a lower operating speed. In practice, a plurality of speed classes are appropriate, for example up to eight speed classes for SDRAMs. The speed class is marked on the housing of the module and sold with this stipulation to customers for incorporation into electronic systems, e.g. computers.
During the fabrication and testing of the integrated circuit, care must be taken to ensure that an integrated circuit originally provided for a lower speed class is not incorrectly marked for a higher speed class. This is made particularly more difficult by the fact that the application of the speed class on the housing of the integrated circuit is usually effected at a different location than the testing of the circuit. The test results are thus previously stored in databases. In order to determine the previously defined speed class for marking the integrated circuit, the database must be accessed and the individual number of the module must be compared with the content of the database.
U.S. Pat. No. 6,130,442 describes a semiconductor memory chip which has registers that are programmable in nonvolatile manner in order to store operating properties, for example the speed. German published patent application DE 44 06 510 describes an integrated circuit with a concomitantly integrated test device.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method and also a circuit configuration for identifying an operating property of an integrated circuit, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which enable a simpler procedure in the course of the identification.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for identifying an operating property of an integrated circuit, which comprises:
ascertaining the operating property of the integrated circuit in a first test run, assigning a first digital identifier to a first value of the operating property thus ascertained, and permanently storing the first value in a first memory element;
subsequently ascertaining the operating property again in a second test run, assigning a second digital identifier to a second value of the operating property thus ascertained, and permanently storing the second value in a second memory element; and
logically combining the digital identifiers in bit-by-bit ORing of bits of the digital identifiers to form an output identifier, and marking the integrated circuit in dependence on the output identifier.
In accordance with an added feature of the invention, the marking step comprises applying a marking to a housing of the integrated circuit.
In accordance with an additional feature of the invention, the operating property ascertained in the first test run or the second test run is a clock frequency of the integrated circuit at which the integrated circuit operates without any faults. For the purpose of ascertaining the fault-free operation, input data are fed to the integrated circuit and output data are tapped off from the integrated circuit as a response to the input data. The output data are then compared with predetermined comparison data.
In accordance with another feature of the invention, the memory elements of the integrated circuit may be preset to mutually complementary values prior to the first test run.
With the above and other objects in view there is also provided, in accordance with the invention, a circuit configuration for identifying an operating property of an integrated circuit, wherein at least two test runs of a functional test of the integrated circuit are performed for ascertaining the operating property, and the operating property is identified in dependence on the at least two test runs, comprising:
a first memory element for permanently storing a digital value depending on the first of the test runs, the first memory element having an output; and
a second memory element for permanently storing a digital value depending on the second of the test runs, the second memory element having an output; and
a logic combination element with a logic OR function, the logic combination element having an input side connected to the output of the first memory element and to the output of the second memory element, and having an output side for outputting a logically combined digital value.
In accordance with a further feature of the invention, the output side of the logic combination element is formed with a plurality of outputs for tapping off the logically combined digital value in parallel.
In accordance with a concomitant feature of the invention, the logic combination element comprises a respective OR gate for each bit position of the digital values, and the OR gates each have an input connected to an output bit of the memory element.
In other words, the objects are achieved, with regard to the method, by means of a method for identifying an operating property of an integrated circuit, wherein, in a first test run, the operating property is ascertained and a first digital identifier assigned to the ascertained value of the operating property is permanently stored in a first memory element and then, in a second test run, the operating property is ascertained again and a second digital identifier assigned to the ascertained value of the operating property is permanently stored in a second memory element and the stored digital identifiers are logically combined by means of bit-by-bit ORing of the bits of the digital identifiers to form an identifier to be output, depending on which the integrated circuit is provided with an assigned marking.
With regard to the circuit configuration, the objects are achieved by means of a circuit configuration for identifying an operating property of an integrated circuit depending on at least two test runs of a functional test of the integrated circuit, which test ascertains the operating property, comprising: a first memory element for permanently storing a digital value depending on the first of the test runs, and a second memory element for permanently storing a digital value depending on the second of the test runs, and a logic combination element which forms a logic OR function and, on the input side, is connected to outputs of the memory elements and, on the output side, is provided with outputs for tapping off a logically combined digital value.
The data representing the operating property, for example the speed class of the integrated circuit, are stored in a nonvolatile manner on the integrated circuit itself. Therefore, a complicated adjustment with a database is not necessary for thi
Greenberg Laurence A.
Infineon - Technologies AG
Le John
Mayback Gregory L.
Nghiem Michael
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