Processing circuit for performing a convolution computation

Details Processing circuit for performing a convolution computation Processing circuit for performing a convolution computation

1996-06-19

1998-10-13

Shah, Alpesh M.

Boots, shoes, and leggings

36472801, 36473601, G06F 1520

Patent

active

058226095

ABSTRACT:
A processing unit for performing convolution computation according to the HARVARD architecture which includes a first and second input register for receiving a first and second operand, a multiplier for multiplying the operand and a Arithmetic and Logic Unit (ALU) circuit. The unit further includes a coefficient storage memory which is used for loading at least one set of coefficients allowing the convolution computation. The memory storage is addressed either from an internal address generator or directly from the internal data bus thereby allowing the possibility to store either coefficients or data into the memory. The flexibility is still increased by the use of a particular set of multiplexing circuits allowing multiple configurations. An internal address generation circuit is used for performing a partial addressing of the set of coefficients thereby providing decimation capability.

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