Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Fusible link or intentional destruct circuit
Reexamination Certificate
2002-08-08
2004-07-20
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Fusible link or intentional destruct circuit
C327S526000
Reexamination Certificate
active
06765427
ABSTRACT:
BACKGROUND OF THE DISCLOSED SYSTEM
1. Field of the Disclosed Circuit
The present disclosed circuit relates to programming antifuses, including those in field-programmable gate arrays (“FPGAs”).
2. Description of the Related Art
Antifuse devices are well known in the integrated circuit art. Antifuse devices comprise a pair of conductive electrodes separated by at least one layer of antifuse material and may include one or more diffusion barrier layers. Prior to programming, antifuses exhibit very high resistance between the two electrodes and may be considered to be open circuits. A programming process disrupts the antifuse material and creates a low-impedance connection between the two conductive electrodes.
Programming circuit overhead for FPGA's takes up a great deal of die space. Reduction of this overhead represents a significant cost savings for manufacturers.
Referring to
FIG. 1
, antifuse
10
is shown coupled between two wiring segments
12
and
14
. If the antifuse
10
is programmed, a connection is created between wiring segments
12
and
14
through the antifuse
10
. First and second steering transistors
16
and
18
are coupled between wiring segment
12
and a source of programming potential V
PP
. Third and fourth steering transistors
22
and
24
are coupled between wiring segment
14
and a ground potential
26
. The steering transistors
16
,
18
,
22
, and
24
are used to steer the programing potentials V
PP
and ground to the antifuse
10
to be programmed. Antifuse
10
is programmed when all four steering transistors are turned on. In the example of
FIG. 1
, V
g
for all of steering transistors
16
,
18
,
22
, and
24
is set at 7 volts.
As may be seen from an examination of
FIG. 1
, third and fourth steering transistors each have small source bias voltages. Steering transistor
24
has a zero-volt source bias because its source is coupled directly to ground and steering transistor
22
has a 1-volt source bias caused by the voltage drop across transistor
24
. Therefore V
GS
for steering transistor
24
will be 7 volts and V
GS
for steering transistor
22
will be 6 volts.
On the other hand, first and second steering transistors
16
and
18
each have a large source bias (V
s
), 3 and 5 volts respectively in the design illustrated in
FIG. 1
where V
PP
is 6 volts. Seven volts is applied to the gates of each of the four steering transistors in this particular design. The gate voltage and large source bias on steering transistors
16
and
18
result in low V
GS
voltages of 2 and 4 volts respectively across those transistors. Due to the low V
GS
voltages, the driver currents in transistors
16
and
18
are low, thus to compensate, the transistors
16
and
18
must be made larger in order to properly program an antifuse. As the size of the steering transistors increase the size of the die increases, thereby increasing costs. Also, with larger transistors, capacitance increases, thereby slowing the speed of the operating circuit.
BRIEF SUMMARY OF THE DISCLOSED CIRCUITS
The disclosed circuits relate to a programming steering circuit comprising a plurality of steering transistors and at least one bootstrapping transistor. The drain of the at least one bootstrapping transistor is coupled to the gate of at least one of the steering transistors.
A better understanding of the features and advantages of the present disclosed system will be obtained by reference to the following detailed description of the disclosed system and accompanying drawings which set forth an illustrative embodiment in which the principles of the disclosed system are utilized.
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pat
Actel Corporation
Cunningham Terry D.
Sierra Patent Group Ltd.
Tra Quan
LandOfFree
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