Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2003-04-24
2004-09-14
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S714000
Reexamination Certificate
active
06790784
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the formation of integrated circuit structures having one or more layers of low dielectric constant (low k) dielectric material. More particularly, this invention relates to a process for plasma treating a layer of low k dielectric material to form, in the surface of the low k dielectric material, a structure useful as an etch stop and/or an etch mask in subsequent formation of a layer of metal interconnects and/or filled vias.
2. Description of the Related Art
The shrinking of integrated circuits has resulted in levels of electrically conductive interconnects being placed closer together vertically, as well as reduction of the horizontal spacing between the electrically conductive interconnects, such as metal lines, on any particular level of such interconnects. As a result, capacitance has increased between such conductive portions, resulting in loss of speed and increased cross-talk. One proposed approach to solving this problem of high capacitance is to replace the conventional silicon oxide (SiO
2
) dielectric material, having a dielectric constant (k) of about 4.0, with another insulation material having a lower dielectric constant to thereby lower the capacitance.
In an article by L. Peters, entitled “Pursuing the Perfect Low-K Dielectric”, published in Semiconductor International, Volume 21, No. 10, Sep. 1998, at pages 64-74, a number of alternate dielectric materials are disclosed and discussed. Included in these dielectric materials is a description of a low k dielectric material having a dielectric constant of about 3.0 formed using a Flowfill chemical vapor deposition (CVD) process developed by Trikon Technologies of Newport, Gwent, U.K. The process is said to react methyl silane (CH
3
—SiH
3
) with hydrogen peroxide (H
2
O
2
) to form monosilicic acid which condenses on a cool wafer and is converted into an amorphous methyl-doped silicon oxide which is annealed at 400° C. to remove moisture.
An article by S. McClatchie et al. entitled “Low Dielectric Constant Oxide Films Deposited Using CVD Techniques”, published in the 1998 Proceedings of the Fourth International Dielectrics For ULSI Multilevel Interconnection Conference (Dumic) held on Feb. 16-17, 1998 at Santa Clara, Calif., at pages 311-318, also describes the formation of methyl-doped silicon oxide by the low-k Flowfill process of reacting methyl silane with H
2
O
2
to achieve a dielectric constant of ~2.9.
The incorporation of such carbon-doped silicon oxide dielectric material into interconnect architecture has been very attractive not only because of the low k properties, but also because of the compatibility with conventional silicon process technologies. Generally these materials remain stable upon annealing at temperatures of up to 500° C. The carbon doped silicon oxide materials are characterized by the structure of amorphous silicon oxide with incorporated methyl groups and hydrogen species, and are also characterized by a reduced density in comparison with conventional silicon oxide that can be explained by the formation of microporosity surrounding the incorporated methyl groups. Furthermore, such hydrocarbon-modified silicon oxide dielectric materials deposited by CVD techniques are also characterized by strong adhesion.
The above-mentioned shrinking of integrated circuits and resultant increase in capacitance and loss in speed has also resulted in a renewed interest in the utilization of higher conductivity materials such as copper for the metal interconnects or “wiring” used in the integrated circuit structure. However, one problem with the use of copper to replace other conductive metals such as aluminum or tungsten in the formation of metal interconnect layers is the difficulty encountered with attempts to apply to the use of copper the conventional process techniques used in forming aluminum or tungsten interconnects wherein a previously deposited layer of metal is patterned by etching the metal layer through a photoresist etch mask photolithographically formed over the metal layer.
Because of these processing difficulties which have confronted attempts to conventionally form copper metal interconnects by patterning a previously deposited layer of copper metal, a different process, referred to as a damascene process, has been developed for forming copper metal interconnects. Instead of forming the metal interconnects first, and then filling the spaces in between the metal interconnects with dielectric material, a dielectric layer is first blanket deposited over the underlying integrated circuit structure, and a pattern of trenches having geometry conforming to the desired pattern of copper metal interconnects is formed through the dielectric layer. After optional formation of thin layers of electrically conductive material over the dielectric layer (and over the surfaces of the trenches therein) to respectively serve as a barrier layer between the dielectric material and the copper, and to facilitate adhesion of the copper layer to the dielectric material, a layer of copper metal is blanket deposited over the dielectric layer. This copper layer fills up all the trenches, as well as depositing on the upper surface of the dielectric layer. The excess copper (and excess barrier/adhesion layers if present) is then removed from the surface of the dielectric material, e.g., by a CMP process, leaving the desired pattern of copper metal interconnects in the trenches in the dielectric layer.
Advantageously, such a process for forming copper metal interconnects is combined with a process for forming copper-filled vias by using a stack of two dielectric layers, with via openings formed in the lower dielectric layer and trench openings formed in the upper dielectric layer. Both the vias and the trenches are then filled with copper during a single copper deposition step. In this process, commonly referred to as a dual damascene process, excess copper is again removed from the surface of the upper layer of dielectric material, usually by a CMP process, leaving a pattern of copper metal interconnects vertically connected electrically by copper-filled vias to the underlying integrated circuit structure.
While the just described damascene and dual damascene processes permit the use of highly electrically conductive copper metal for both via filling and metal interconnect formation, integrated of such processes with the use of layers of low k dielectric materials has resulted in the formation of further problems. The damascene processes, and in particular the dual damascene process, require the use of masking and etch stop layers which may necessitate the use of layers of non-low k dielectric layers between and over the layers of low k dielectric material, thereby undesirably raising the overall dielectric constant of the resultant compound layer of dielectric materials. Furthermore, to ensure selectivity of the mask or etch stops materials during the etch step or steps, it has, in the past, been necessary to use different dielectric material such as silicon nitride or silicon carbide for the mask and/or etch stop layers. This further complicates the deposition portion of the process, since the semiconductor substrate on which the integrated circuit structure is formed may have to be moved back and forth between several deposition chambers. Adhesion problems between dielectric layers may also arise when layers of materials such as silicon nitride and silicon carbide are introduced into the structure.
It would, therefore, be desirable to form an integrated circuit structure with both low k dielectric material and copper metal interconnects and/or copper-filled vias wherein any permanent introduction of other material such as silicon nitride or silicon carbide as masks or etch stops is avoided, and increases in the dielectric constant of the resultant compound layer of dielectric materials is minimized, thereby optimizing the benefits of the combined use of low k dielectric materials and copper-filled vias and/or copper metal interc
Catabay Wilbur G.
Hsia Wei-Jen
Cuneo Kamand
Kilday Lisa
LSI Logic Corporation
Taylor John P.
LandOfFree
Plasma treatment of low dielectric constant dielectric... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Plasma treatment of low dielectric constant dielectric..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Plasma treatment of low dielectric constant dielectric... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3252629