One mask PNP (or NPN) transistor allowing high performance

Details One mask PNP (or NPN) transistor allowing high performance One mask PNP (or NPN) transistor allowing high performance

2002-09-13

2004-09-28

Lee, Hsien Ming (Department: 2823)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

C438S313000, C438S318000, C438S322000, C438S323000, C438S373000

Reexamination Certificate

active

06797577

ABSTRACT:

FIELD OF INVENTION
The present invention relates to improved methods for manufacturing integrated circuit devices and more particularity to improved methods related to the manufacture of high performance bipolar transistors fabricated with a BiCMOS and CMOS process.
BACKGROUND OF THE INVENTION
An accelerating trend in the integrated circuit industry is the merging of analog and digital functions onto the same semiconductor substrate. In addition, transistor components located on these devices are challenged to achieve higher performance characteristics, such as higher cut off frequencies, higher transistor gains, lower collector resistance, etc.
Bipolar junction transistors are one of the older types of transistors which can act either as an amplifier or a switching device and are widely used in discrete circuits as well as integrated circuits. Bipolar junction transistors provide high current drive capabilities, are very useful as a constant current source and as an active load in many analog/digital applications. Bipolar junction transistor characteristics are so well understood, that circuit design using bipolar junction transistors is a relatively easy task. In addition, circuit designs using bipolar junction transistors can obtain performance results that are remarkably predictable and quite insensitive to variations in device parameters. Alternatively, complementary metal-oxide semiconductor (CMOS) devices composed of P and N-channel field effect transistors offer low power consumption, high packing density and dynamic memory storage capabilities.
With the advantages of both bipolar junction and CMOS transistor families in mind, the current industry trend is to incorporate both CMOS and bipolar junction transistors onto the same semi conductor substrate. In this manner the advantages of both families of transistors are realized. However, there are disadvantages to this approach in that as circuit devices are downscaled, bipolar junction transistors become more difficult (and thus more expensive) to fabricate. This is especially true if the device is expected to have high performance (bipolar junction transistor) characteristics and yet incorporate optimized CMOS transistors.
To meet the industry needs, a method for providing high performance bipolar junction transistors in a cost effective manner, when incorporating CMOS transistors on a device needs to be addressed (e.g., a cost effective method to form high performance bipolar junction transistors in a BiCMOS and CMOS process).
One prior art method addressing the cost involved with bipolar junction transistor fabrication on a BiCMOS and CMOS device is illustrated in
FIGS. 1A-1D
. This process involves the fabrication of vertical bipolar junction transistors within a BiCMOS and CMOS process flow. These transistors are typically fabricated by forming a deep N well
12
within a substrate
10
. A P-type collection region
11
is then formed within the deep N-well
12
. This act, or event, is followed by the formation of isolation regions
13
. All the acts, or events, mentioned so far, are performed using masking operations which would also be utilized during CMOS transistor formation (e.g, at to this point in the BiCMOS and CMOS process, no additional masking operations are required to form a bipolar transistor on the device).
Photoresist
14
is applied to the surface of the device in preparation for a pattern to be formed. This pattern is formed using an extra mask
15
(e.g., a mask not normally used in a BiCMOS and CMOS transistor forming process), which blocks UV radiation and removes exposed portions of the photoresist
14
. The pattern is then used to implant an N-type base
16
. After this act or event, the pattern is removed (e.g., the photoresist
14
is removed).
Next, N-type base contact
17
, P-type emitter
18
, and P-type collector contact
19
are formed with source/drain implants using masking operations which are utilized during CMOS transistor formation. Finally an isolation region
20
is formed between the base
17
contact implant and the emitter contact implant
18
in order to provide isolation between the two regions during subsequent metallization connections.
Advantages of this prior art method are the relative low cost since only one extra mask
15
is required to form the base of the transistor, however, this bipolar junction transistor formation method suffers a significant disadvantage in that it has poor performance characteristics. In other words the process is well optimized for CMOS transistors, but not for bipolar junction transistors due to a non-optimized collector region
11
. In general, this prior art process suffers from high doping at implant surfaces resulting in low base-collector breakdown voltage, high base-collector capacitance, and low early voltage (e.g., a measure of a transistor's output node properties and how ideal these properties are when the transistor is used as a current source, proportional to the base collector capacitance). The process also suffers from low dopant concentration at larger depths that results in a high collector resistance and high parasitic transistors gains. Some reasons for these low bipolar junction transistor performance characteristics result from restrictions associated with the BiCMOS and CMOS process (such as the tuning process of the collector for source/drain implants, etc.) and the method's inability to implant high dopant concentrations deep into the collector region.
A second prior art method results in high bipolar junction transistor performance characteristics, however this method requires extra masking operations (and hence extra costs) as illustrated in
FIGS. 2A-2E
.
In
FIG. 2A
, a photoresist
30
is applied to the surface of the device in preparation for a pattern to be formed. This pattern is formed using an extra mask
31
(e.g., a mask not normally used in the BiCMOS and CMOS process), which blocks UV radiation and removes exposed portions of the photoresist
30
. The pattern is then used to form a buried P-type collector region
32
using a high energy ion implantation (or another similar method) within a deep N-well
33
. The pattern is then removed (e.g., the photoresist
30
is removed).
This act, or event, is followed by the formation of isolation regions
34
(e.g., shallow trench isolation (STI) regions) using techniques which are normally used within a BiCMOS and CMOS transistor formation process. Next, photoresist
45
is applied to the surface of the device in preparation for a second pattern to be formed. This pattern is formed using a second extra mask
36
(e.g., a mask not normally used in a BiCMOS and CMOS process), which blocks UV radiation and removes exposed portions of the photoresist
45
. The pattern is then used to form deep P-wells
35
which will couple the P-type collector source/drain contact implants (described below) with the deep buried P-type collector region
32
. After this act or event, the pattern is removed (e.g., the photoresist
45
is removed).
Next, photoresist
46
is applied to the surface of the device in preparation to form a third pattern. This pattern is formed using a third extra mask
38
(e.g., a mask not normally used in the BiCMOS and CMOS process), which blocks UV radiation and removes exposed portions of the photoresist
46
. The pattern is then used to form a highly doped, N-type base
39
via implantation. After this act or event, the pattern is removed (e.g., the photoresist
46
is removed).
Next, an N-type base contact
40
, P-type emitter contact
41
, and P-type collector contact regions
42
are formed using masking operations that are utilized to form source/drain regions during CMOS transistor formation. Note that the P-type collector source/drain contact implants
42
are coupled to the buried P-type collector
32
via deep P-wells
35
, providing lower transistor collector resistance than the prior art transistor structure of FIG.
1
D. Finally an isolation region
43
is formed between the base contact region
40
and the emitter contact region

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