Pulse or digital communications – Transceivers
Reexamination Certificate
2000-05-12
2004-09-28
Liu, Shuwang (Department: 2634)
Pulse or digital communications
Transceivers
C375S231000, C375S375000, C375S295000, C379S406120
Reexamination Certificate
active
06798827
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is generally directed to high-speed Ethernet local area networks (LANs) and, more specifically, to a DC offset correction system for use in a full-duplex transceiver for a gigabit Ethernet network.
BACKGROUND OF THE INVENTION
The rapid proliferation of local area network (LANs) in the corporate environment and the increased demand for time-sensitive delivery of messages and data between users has spurred development of high-speed (gigabit) Ethernet LANs. The 100BASE-TX Ethernet LANs using category-5 (CAT-5) copper wire and the 1000BASE-T Ethernet LANs capable of one gigabit per second (1 Gbps) data rates over CAT-5 data grade wire require new techniques for the transfer of high-speed symbols.
The transfer of high-speed symbols over an Ethernet LAN requires full-duplex gigabit (Gbps) Ethernet transceivers which transmit and receive data over category-5 copper wire at the 1 Gbps data rate. This full-duplex data transfer occurs over four twisted pairs at 125 mega-symbols (125 Mbaud) per second per pair, which is the same as a transfer rate of 500 mega-symbols (Mbaud) per second in each direction.
In an exemplary system, data is transmitted using a five-level pulse amplitude modulation (PAM-5) technique. In PAM-5, data is represented by five voltage levels, designated as an alphabet symbol {A} represented by data bits with the symbol alphabet having values of −2, −1, 0, 1, 2 volts, for example. The actual voltage levels may differ from these five levels. At each clock cycle, a single one-dimensional (1D) symbol is transmitted on each wire. The four 1D symbols traveling in one direction on each of the conductor pairs at a particular sample time k are considered to be a single four-dimensional (4D) symbol. In addition, extra channel symbols represent Ethernet control characters. Therefore, five level PAM (PAM-5) with either a parity check code or trellis coding is often utilized in Gigabit Ethernet transmission.
At 125 Mbaud, each 4D symbol needs to transmit at least eight bits. Therefore, 256 different 4D symbols plus those required for control characters are required. By transmitting a 4D PAM-5 symbol alphabet, there are 5
4
=625 possible symbols. This number of symbols allows for 100% redundancy in the data as well as for several control codes. Symbol alphabets having more than five symbols yield even greater redundancy.
Another technique for transferring data at high rates is known as non-return to zero (NRZ) signaling. In NRZ, the symbol alphabet {A} has values of −1 and +1 volts. A Logical 1 is transmitted as a positive voltage, while a Logical 0 is transmitted as a negative voltage. At 125 mega-symbols per second, the pulse width of each NRZ symbol (the positive or negative voltage) is 8 nano-seconds.
Another modulation method for high speed symbol transfer is known as multi-level transmit-3 (MLT-3) which uses three voltage levels for the transfer of data. This American National Standard Information (ANSI) approved modulation technique is used for the transfer of data over a 100BASE-TX network using unshielded twisted pairs.
In MLT-3 transmission, a Logic 1 is transmitted as either a −1 or a +1 voltage while a Logic 0 is transmitted as a 0 voltage. Thus, the transmission of two consecutive Logic 1s does not require an MLT-3 system to pass data through zero. The transmission of an MLT-3 logical sequence (1, 0, 1) results in transmission of the symbols (+1, 0, −1) or (−1, 0, +1), depending on the symbols transmitted prior to this sequence. If the symbol transmitted immediately prior to the sequence is a +1, then the symbols (+1, 0, −1) are transmitted. If the symbol transmitted before this sequence is a −1, then the symbols (−1, 0, +1) are transmitted. If the symbol transmitted immediately before this sequence is a 0, then the first symbol of the sequence transmitted will be a +1 if the previous Logic 1 is transmitted as a −1 and will be a −1 if the previous Logic 1 is transmitted at +1.
The signal-to-noise ratio (SNR) required to achieve a particular bit error rate is higher for MLT-3 signaling than for two level systems. The advantage of the MLT-3 system, however, is that the energy spectrum of the emitted radiation from the MLT-3 system is concentrated at lower frequencies and therefore more easily meets Federal Communications Commission (FCC) radiation emission standards for transmission over twisted pair cables.
Other modulation schemes for multi-symbol coding can also be utilized, including quadrature amplitude modulation (QAM). In QAM schemes, for example, the symbols are arranged on two-dimensional (real and imaginary) symbol constellations (instead of the one-dimension constellations of the PAM-5 or MLT-3 symbol alphabets.)
These multi-level symbol representations were not needed prior to the development of higher speed computer networks, since data could be transferred between computers at sufficient speeds and accuracy as binary data. However, the higher gigabit per second Ethernet data rate and other communications schemes requires transmitters and receivers capable of transmitting and receiving data over multiple twisted copper pair using larger symbol alphabets (i.e., 3 or more symbols). There is also a need for transceiver (transmitter/receiver) systems that operate at high symbol rates while maintaining low bit error rates (BERs).
As in other communications systems, the transmission cable (or channel) connecting the transmitter and receiver distorts the shape of the transmitted symbol stream. Each symbol transmitted is diffused in the transmission process so that it is commingled with symbols being transmitted at later transmission times. This effect is known as “intersymbol interference” (ISI) and is a result of the dispersive nature of the communication cable. The transmitted waveform is further changed by the cable transmission characteristics, noise which is added over time, and interfacing devices such as transformers, for instance.
When the high-speed signal is received at the transceiver, it is further modified by the physical and operating characteristics of the receiving transceiver. For instance, the impedance that may be seen by the transceiver front-end not only includes the impedance of the cable and the transformer that couples the cable to the transceiver front-end, but also the impedance of on-board traces and input/output structures. Input/output structures include electrostatic discharge protectors, input/output cells, and the like, that may reside on an integrated circuit before the transceiver front-end components.
Therefore, there is a need in the art for improving the performance of full-duplex transceivers for operation at gigabit per second data rates across local area networks. There is a further need in the art for improving the performance of full-duplex transceiver front-ends to compensate for operational changes due to cable and circuit characteristics as well as the lengths of connecting cable. In particular, there is a need for improved transceiver front-ends which accommodate changes due to manufacturing processes and environmental changes across time. More particularly, there is a need in the art for a high performance full-duplex transceiver front-end which incorporates a system for improving performance by cancelling echos and correcting for signal offsets, as well as adjusting performance due to direct current and data dependent drifts and off-sets.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide, for use in a transceiver comprising front-end analog signal processing circuitry capable of operating in a high frequency Ethernet local area network (LAN), an apparatus for correcting an input DC offset signal generated in the front-end analog signal processing circuitry. In an advantageous embodiment of the present invention, the apparatus compr
Liu Shuwang
National Semiconductor Corporation
Zheng Eva
LandOfFree
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