Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2002-09-18
2004-04-06
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189020
Reexamination Certificate
active
06717885
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to apparatus and methods for memory systems. More specifically, the present invention relates to apparatus and methods for writing process in a memory system.
2. Description of the Background Art
Dynamic Random Access Memory (DRAM) has evolved from asynchronous DRAM to synchronous DRAM. For example, Fast-Page DRAM and Extended Data Output (EDO) DRAM have evolved to Synchronous Dynamic Random Access Memory (hereinafter abbreviated to SDRAM). Currently, high speed memory banks generally use synchronous source methods for achieving data transmission. By way of an example, Double Data Rate dynamic random access (hereinafter abbreviated to DDR SDRAM) memory bank is one of the methods. In addition, these high speed memory banks require differential signals for data transmission. Therefore, real high access speed for DRAMs requires differential signaling. It is desirous to combine source synchronization with differential signaling.
Furthermore, DRAM market tends to be outpaced in bandwidth by such elements as processor, I/O devices, or graphic add-on devices. This deficiency in bandwidth becomes especially significant for high volume data transfer applications such as Internet applications.
In order to further improve the bandwidth, schemes such as Double Data Rate (DDR), Quad Band Memory (QBM), and Quad Data Rate (QDR) are used for transmitting two or four units of data as compared to a single unit for the baseline rate. Further, the above has the advantage of using existing low-cost technology for increasing the bandwidth.
However, prior art memory systems such as QBM systems tend to have a reduced upper limit in clock frequency because of various factors such as skews between various timing signals or sequences. These skews deviate from the idealized timing sequence and limit further increases in clock frequency. Thereby a further increase in speed is rendered impractical.
As can be seen, there is a need for an improved apparatus and methods wherein memory access speed can be further increased.
SUMMARY OF THE INVENTION
In the present invention, an improvement on memory access is provided by extending the data valid window of a sequence of data segments using a latch circuit.
The present invention further improves memory access by providing a delay circuit for related timing diagrams which are otherwise not in correspondence with each other.
Accordingly, a switching circuit for improving memory writing timing sequence is provided. The switching circuit is coupled to a memory controller, a first DDR memory bank, and a second DDR memory bank. The switching circuit includes a data writing path for providing a plurality of data segments, wherein each data segment has the same valid window. The switching circuit further includes a first latch and a second latch. The first latch is disposed within the data writing path and in communication with the first DDR memory bank. The first latch extends the valid window of the odd numbered data segments of the plurality of data segments. The second latch is disposed within the data writing path and in communication with the second DDR memory bank. The second latch extends the valid window of the even numbered data segments of the plurality of data segments.
Accordingly, a switching circuit for improving memory writing timing sequence is provided. The switching circuit is coupled to and interposed between to a memory controller, a first memory bank, and a second memory bank. The switching circuit is used for transforming a first set of data segments coming from the memory controller into a second set of memory data segments. The second set of memory data segments are transmitted to the memory banks. The rate of transmission of the second set of memory data is less than the rate of transmission of the first set of memory data. The switching circuit includes a latch circuit for receiving a latching signal, wherein the latching signal is generated using a logical combination among a plurality of memory selection signals coming from the memory controller. The latching signal controls the latch circuit to hold the first set of data segments and to output the second set of memory data segments, thereby causing the data valid windows of the second set of memory data segments to be greater than the data valid windows of the first set of data segments.
Accordingly, a method for improving memory writing timing sequence is provided. The method includes the steps of receiving a plurality of data segments, wherein each data segment has the same data valid window; extending the data valid windows of the odd numbered data segments of the plurality of data segments and transmitting the same to a first memory; and extending the data valid windows of the even numbered data segments of the plurality of data segments and transmitting the same to a second memory
These and other features, aspects and advantages of the present invention will become better understood with reference to the following drawings, description and claims.
REFERENCES:
patent: 5886553 (1999-03-01), Matsui
patent: 6445642 (2002-09-01), Murakami
Nguyen Tan T.
Patents J. C.
Via Technologies Inc.
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