Fishing – trapping – and vermin destroying
Patent
1994-04-28
1996-04-16
Monin, Jr., Donald L.
Fishing, trapping, and vermin destroying
437 48, 437 59, 437907, 257 66, 257344, H01L 2701, H01L 2904, H01L 29784
Patent
active
055082165
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The present invention relates to a thin film transistor, a solid device such as a semiconductor device, a display device such as a liquid crystal display panel, and a manufacturing method of a thin film transistor. More particularly, the present invention pertains to a technique of improving electrical characteristics of a thin film transistor.
In an active matrix substrate of a liquid crystal display panels, for example, a thin film transistor on board as its switching element is shown in FIG. 20. The transistor is formed in such a way that after a gate oxidation film 2203 is formed on a silicon layer 2202 on the surface of a substrate 2201, a source area 2205 and a drain area 2206 are self-aligned by implanting ions to silicon layer 2202 with a gate electrode 2204 on the surface of 2203 as a mask so as to make a part of the silicon layer electrically-conductive. However, there is a problem associated with the thin film transistor having a structure shown in FIG. 20. As shown by a solid line L3 in FIG. 21, a large intense drain current flows even when a negative gate voltage is applied (in off state) to a gate electrode 2204. This could be understood as a phenomenon in which at the end of drain area 2206 which is biased in the opposite direction, a pn-junction breaks and a hole is implanted. The intensity of a drain current is dependent on the voltage applied between gate electrode 2204 and drain area 2206 and the density of a trap energy level in a silicon layer corresponding to drain area 2206 and an end of gate electrode 2204 near drain area 2206. Accordingly, a structure may be used where a ratio of on-off current is increased by employing a drain structure whose field strength is weakened (LDD structure) by establishing a low concentration area at an end of a drain area corresponding to an end of a gate electrode. In order to manufacture a thin film transistor with this LDD structure, the following manufacturing method has been adopted conventionally. First, as is shown in FIG. 22A, after a pattern 2402 comprising a silicon film has been formed on the surface of a substrate 2401, the pattern is covered with a gate insulation film 2403, on the surface of which an electrically-conductive film 2404 is formed and constitutes a gate electrode.
Second, as is shown in FIG. 22B, a resist pattern 2405 is formed on an electrically-conductive film 2404 by employing a photolithography technique. By performing an etching selectively, with the resist pattern 2405 used as a mask, a gate electrode 2406, which is thinner than the resist pattern, is formed.
Third, in an ion implantation method, by implanting impurities either as a donor or as an acceptor, and with an amount of as much as 1.times.10.sup.15 cm.sup.-2 for instance, a source area 2407 and a drain area 2408 are formed in a self-aligned way, as in FIG. 22C. The area where ions are not implanted on account of gate electrode 2406 and resist pattern 2405 becomes a channel area 2409.
Fourth, resist pattern 2405 is removed. In order to form an LDD structure, as is shown in FIG. 22D, by implanting impurities of about 1.times.10.sup.14 cm.sup.-2 in an ion implantation method, with gate electrode 2406 as a mask, low concentration areas 2410 and 2411 are formed in an area in alignment with the ends of gate electrode 2406.
However, in the manufacturing method of a thin film transistor with a conventional LDD structure, after gate electrode 2406 is formed, then source area 2407, drain area 2408 and low concentration areas 2410 and 2411 are formed. Thus, when the silicon film to which impurities are implanted is heat-treated at about 1000.degree. C. to activate the impurities, gate electrode 2406 is also heated. Therefore, only materials having high heat resistance such as a silicon compound can be used for gate electrode 2406, which is at the expense of the electric resistance and other characteristics of the gate electrode. In such a case, if signals are transmitted along the wires formed simultaneously with gate electrode 2406, as in an
REFERENCES:
patent: 5266504 (1993-11-01), Blouse et al.
patent: 5308998 (1994-05-01), Yamazaki et al.
patent: 5323042 (1994-06-01), Matsumoto
Monin, Jr. Donald L.
Seiko Epson Corporation
Tsiang Harold T.
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