Electrostatic discharge protection circuit

Details Electrostatic discharge protection circuit Electrostatic discharge protection circuit

2002-03-17

2004-09-07

Leja, Ronald (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C257S494000

Reexamination Certificate

active

06788507

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a protection circuit, and more particularly, to an electrostatic discharge (ESD) protection circuit.
2. Description of the Prior Art
Electrostatic discharge (ESD) usually occurs in semiconductor devices. The ESD phenomenon occurs when excess charges are transmitted from the input/output (I/O) pin to the integrated circuit too quickly, damaging the internal circuit. To solve such a problem, manufacturers normally build an electrostatic discharge (ESD) protection circuit between the internal circuit and the I/O pin. The ESD protection circuit is initiated before the pulse of electrostatic discharge enters the internal circuit, discharging the excess charges, and thus ESD-related damage is decreased.
With the continuing scaling-down of semiconductor integrated circuit (IC) device dimensions, not only are channel lengths being shortened, gate oxide layers becoming thinner, and junction depths getting shallower, but also dopant concentrations of wells are rising in deep sub-micron complementary metal-oxide-semiconductor (CMOS) processes. All of these developments make IC products more susceptible to damage from electrostatic discharge. Consequently, more effective ESD protection circuits need to be built on-chip to discharge ESD-induced currents, and hence protect the IC against any ESD-related damage. In short, ESD robustness for IC products needs to be improved. To make an effective ESD protection circuit, an adequate ESD protection device must first be designed and manufactured into the ESD protection circuit. A very direct and effective solution is to increase the discharge path for ESD-induced current by enlarging the area of ESD protection device. However, the chip area occupied by the ESD protection device should not be excessive, lest the ESD protection device prevent further size reductions of the chip.
The prior art method of preventing electrostatic breakdown caused by electrostatic pulse is to utilize a parasitic diode in a metal-oxide semiconductor field effect transistor (MOSFET) as an ESD protection device. Please refer to FIG.
1
.
FIG. 1
is a circuit diagram of a prior art ESD protection circuit
20
for protecting an internal circuit
10
. As shown in
FIG. 1
, the ESD protection circuit
20
is electrically connected between the internal circuit
10
and a bonding pad
12
. The bonding pad
12
is utilized as a medium of electronic signals between the outside and the internal circuit
10
. When electrostatic charges enter the internal circuit
10
through the bonding pad
12
, the ESD protection circuit
20
protects the internal circuit
10
from being burnt-out due to the high electrostatic current. The ESD protection circuit
20
comprises a P-type metal-oxide semiconductor (PMOS)
22
and an N-type metal-oxide semiconductor (NMOS)
24
. The drains of the PMOS
22
and NMOS
24
are tied together and connected to the internal circuit
10
and the bonding pad
12
via a conducting wire
14
. The source of the PMOS
22
is connected to both the gate of the PMOS
22
and a V
DD
power terminal. The source of the NMOS
24
is connected to both the gate of the NMOS
24
and a V
SS
power terminal. A first parasitic diode
26
is formed in the PMOS
22
and a second parasitic diode
28
is formed in the NMOS
24
.
When an ESD voltage is applied on the ESD protection circuit
20
, across any two of the V
DD
power terminal, the bonding pad
12
, and the V
SS
power terminal to produce ESD current, the ESD current is quickly discharged through the turned on first parasitic diode
26
, the turned on second parasitic diode
28
, the snapback breakdown of PMOS
22
, or the snapback breakdown of NMOS
24
. For example, when an user carrying electrostatic charges contacts the V
DD
power terminal and the bonding pad
12
simultaneously, making the potential of the bonding pad
12
greater than the potential of the V
DD
power terminal, the first parasitic diode
26
is turned on to discharge the electrostatic charges quickly. When an user carrying electrostatic charges contacts the bonding pad
12
and the V
SS
power terminal simultaneously, making the potential of the bonding pad
12
greater than the potential of the V
SS
power terminal, a snapback breakdown of the NMOS
24
occurs to discharge the electrostatic charges quickly. The above mentioned snapback breakdown phenomenon can be referred to in U.S. Pat. No. 5,804,860. However, with the continuing scaling-down of semiconductor integrated circuit (IC) device dimensions, the gate oxide layer in a MOSFET is becoming thinner. As a result, the snapback breakdown phenomenon is difficult to control. In addition, many factors are involved in preventing ESD-related damage to the internal circuit and preventing the ESD protection circuit from being burnt-out due to a high ESD current. The spacing between drain and gate, the adapting of a salicide block (SAB), and the dopant concentration of wells all must be considered when designing the ESD protection circuit.
SUMMARY OF INVENTION
It is therefore a primary objective of the claimed invention to provide an ESD protection circuit, especially an ESD protection circuit that utilizes an equivalent zener diode, formed by a simpler ion implantation method, to provide a path to discharge ESD current.
According to the claimed invention, the ESD protection circuit is formed on a P-type substrate and is disposed between a bonding pad and an internal circuit formed on the P-type substrate. The ESD protection circuit is connected to the bonding pad, a first power supply terminal (V
DD
) a second power supply terminal (V
SS
) and the internal circuit and includes a P-type metal-oxide semiconductor (PMOS) and an N-type metal-oxide semiconductor (NMOS).
The PMOS includes a P
+
guard ring, a first N
+
diffusion region, a first N-well, and a first doped region. The P
+
guard ring is formed on the P-type substrate. The first N
+
diffusion region is formed on the P-type substrate and is surrounded by the P
+
guard ring, but is not in contact with the P
+
guard ring. The first N-well is formed on the P-type substrate and is contact with the first N
+
diffusion region. The first doped region is formed below the P
+
guard ring and the first N
+
diffusion region, and is contact with the P
+
guard ring and the first N
+
diffusion region to form a first equivalent zener diode.
The NMOS includes an N
+
guard ring, a first P
+
diffusion region, a second N-well, and a second doped region. The N
+
guard ring is formed on the P-type substrate. The first P
+
diffusion region is formed on the P-type substrate and is surrounded by the N
+
guard ring, but is not in contact with the N
+
guard ring. The second well is formed below the N
+
guard ring and is in contact with the N
+
guard ring. The second doped region is formed below the N
+
guard ring and the first P
+
diffusion region, and is in contact with the N
+
guard ring and the first P
+
diffusion region to form a second equivalent zener diode.
It is an advantage of the claimed invention to utilize an ion implantation process to form the P-type doped region or the N-type doped region below the guard ring and the well pick-up. The equivalent zener diode is formed on the P-type substrate to discharge the ESD current. Additionally, the claimed invention ESD protection circuit is more easily made since it is not necessary to consider the various processing factors that affect the snapback breakdown phenomenon.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.


REFERENCES:
patent: 5130760 (1992-07-01), Matzen et al.
patent: 5500546 (1996-03-01), Marum et al.
patent: 5631793 (1997-05-01), Ker et al.
patent: 5691554 (1997-11-01), Matth

Affiliated with

Also associated with

Rating

Electrostatic discharge protection circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electrostatic discharge protection circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electrostatic discharge protection circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3247835