Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Electrical signal parameter measurement system
Reexamination Certificate
2002-06-27
2004-09-21
Barlow, John (Department: 2863)
Data processing: measuring, calibrating, or testing
Measurement system in a specific environment
Electrical signal parameter measurement system
C713S310000
Reexamination Certificate
active
06795781
ABSTRACT:
FIELD
The present invention relates generally to the field of power management in a computer and, more specifically, to power management in an electronic device.
BACKGROUND
Power consumption by computer processors increases every generation. It is becoming more important to mange the amount and rate of power consumption. A successful power management scheme could improve power performance efficiency and help reduce average die temperature. A computer processor, also known as a central processing unit (“CPU”), is comprised of several functional units such as registers, arithmetic logic units, flopping point units, etc. These functional units consume power when in use.
Some conventional methods have been employed to try to manage, and consequently conserve, power in a CPU. For example, some conventional methods recognize that a large amount of power consumed by the CPU is proportional to the frequency of the clock sequencing the operation of the CPU. Because CPUs spend a large percentage of time idling (in idle loops, waiting for input-output operations to complete, etc.), some power management systems have concentrated on reducing CPU clock speed during periods of CPU inactivity and during periods when the operations performed by the CPU do not require high clock frequencies. However, these methods only slow down the power-loss by slowing down the clock frequencies, still allowing large amounts of power to be wasted. Also, these methods are characterized by educated guess work. For example, these methods must recognize when the functional units are actually idling. To do this, the methods must monitor functional units to ensure that the functional units are not actually executing instructions before slowing down the clock frequencies, so as not to adversely affect the functional units performance. However, monitoring the functional units may require waiting for several clock cycles to ensure that the functional unit is truly idle. Power is lost during the wait time. Additionally, when the functional unit must perform again, several clock cycles of delay may be required to get the clock frequencies back up to speed, thus slowing down performance speed of the processor.
Other methods attempt to power-down functional units when they are idle. These methods, however, are also characterized by guesswork just as are the methods for slowing the clock frequencies. These methods must monitor the functional units for idling. As the method monitors for idle cycles, however, it must wait a certain number of clock cycles to unsure that functional units are truly idle, then power them down. The wait time leads to lost power. Additionally, once powered-down, the functional units may experience a delay time in powering back up. The power-up delay time means that the instructions may not be performed as quickly as they could have if the functional unit had never been powered-down. Thus, this delay time can also adversely affect CPU performance speed immensely.
REFERENCES:
patent: 6219796 (2001-04-01), Bartley
patent: 6430693 (2002-08-01), Lin
Aldridge Tomm
Bodas Devadatta V.
Barlow John
Cherry Stephen J.
LandOfFree
Method and apparatus for compiler assisted power management does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for compiler assisted power management, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for compiler assisted power management will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3247828