Semiconductor device and laminated leadframe package

Details Semiconductor device and laminated leadframe package Semiconductor device and laminated leadframe package

2002-08-12

2004-03-30

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S123000

Reexamination Certificate

active

06713317

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates in general to semiconductor devices and, more particularly, to small footprint packaged integrated circuits.
Electronic system manufacturers continue to demand components with higher performance and reliability along with a reduced physical size and manufacturing cost. In response, semiconductor manufacturers are developing techniques to reduce the component size and cost by mounting multiple components on a single leadframe that is encapsulated to form a single integrated circuit package.
The size of an integrated circuit package is determined in part by the minimum feature size of the package's leadframe, which sets the width and spacing of the leads. The minimum feature size typically is about equal to the thickness of the leadframe metal, which is a function of the mechanical requirements of the package and the electrical and thermal specifications of the encapsulated circuit. For example, high power circuits often require thicker leadframe metal to support high current levels and adequately dissipate heat generated by the circuit. Furthermore, the width and spacing of the leads needed to handle the increasing power, thermal dissipation, and speed requirements place further restrictions on reducing the size of an integrated circuit package.
Small interconnect feature sizes previously have been achieved by mounting the circuitry on an interposer. An interposer is a type of printed circuit board with layers of thin metal foil sandwiched between dielectric layers and etched to produce the interconnect lines that electrically connect to the components mounted on the interposer. The metal foil is thin, so small feature sizes are achievable. However, for high current devices, the interposer's thin metal lines must be made wide, which offsets the benefit of using a thin foil layer and increases the package footprint. For high power applications, the high thermal resistance of the interposer's thin metal foil results in inadequate heat removal. Moreover, interposers have a high fabrication cost, which further limits their application.
Other devices such as power transistors often require multiple leads in order to provide sufficient current carrying capacity. Such multiple leads also function as a means for providing a thermal conduction path to carry heat away from the die. Such multiple leads are inefficient, introduce excessive costs, and increased defect opportunities.
Power transistors and other devices are also packaged in ball grid array (BGA) packages. Power transistors in BGA packages have the source connection made on the bottom of the die, that is the side of the package facing the customer printed circuit board. Thus heat conducted away from the die by the source connection is undesirably propagated to the customer printed circuit board. It would be an advantage in many devices to propagate the heat away from the printed circuit board. Furthermore, BGA packaged devices require additional processing steps to form bumps on the semiconductor die bonding regions, which is expensive.
Hence, there is a need for a semiconductor device and package that can house multiple components in a small footprint, has a high current and thermal dissipation capability and a high reliability while maintaining a low manufacturing cost.


REFERENCES:
patent: 6110823 (2000-08-01), Eldridge et al.
patent: 6350668 (2002-02-01), Chakravorty
patent: 6424541 (2002-07-01), Fazelpour
patent: 0706208 (2002-12-01), None
http://www.amkor.com/enablingtechnologies/SIP/index.cfm Amkor Technology, System in Package (SiP) Technology Solution Sheet, at www.amkor.com.

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