Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing
Reexamination Certificate
2000-09-13
2004-04-20
Von Buhr, Maria N. (Department: 2125)
Data processing: generic control systems or specific application
Specific application, apparatus or process
Product assembly or manufacturing
C700S097000, C700S266000, C438S115000, C438S906000, C134S001300, C134S902000
Reexamination Certificate
active
06725119
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a process for designing a cleaning-apparatus line configuration in a manufacturing process for a semiconductor device, and a cleaning apparatus optimized for its line configuration according to the designing process.
2. Description of the Prior Art
In a process for manufacturing a semiconductor device, a variety of pretreatment and cleaning procedures are conducted before some steps such as forming a conductive material film and an insulating film on a semiconductor surface and a conductive material film on a dielectric material film. Such pretreatment/cleaning procedures include removing undesired or remaining materials from a previous step, e.g., an undesired photoresist mask, removing particles or residues inevitably remaining after a step such as dry etching; and exposing a clean surface used in the next step, e.g., removing an undesired oxide film formed on a surface of a semiconductor device or conductive material. Each pretreatment/cleaning has a specific purpose depending on steps before and/or after the procedure, and conducted with an appropriate means. When cleaning by selectively removing a film, particles or residues remaining in a small amount on a surface, a variety of etchants may be sometimes used to slightly etch the whole surface. Alternatively, a particular substance is selectively dissolved under mild conditions. Furthermore, two or more of these means may be combined to conduct a wet process meeting a requirement in each case.
A process for manufacturing a semiconductor device comprises several etching steps, some of which employ wet etching rather than dry etching in the light of suitability. These various wet etching steps themselves selectively dissolve and remove a target material layer or a given area, and at the end of etching, an etchant on a surface is thoroughly cleaned/removed.
In a wet process such as wet etching, cleaning and pretreatment, a whole substrate is immersed in an etchant for chemical treatment. An etchant employed in the wet process is usually used for removing adhering contaminants during another step or dissolving a film itself such as a resist or natural oxide film; i.e., for primarily dissolving and removing a substance of interest. However, a new material such as a special metal has been recently employed in a semiconductor device, so that as a special case, a substance not of interest may be concomitantly dissolved in an extremely small amount. Thus, besides ion species generated mainly after dissolving a substance of interest, there may be present ion species generated by a concomitant dissolution reaction in a very small amount in an etchant. For example, when dissolving and removing an oxide film on the rear face of a silicon substrate as a pretreatment, a very small amount of a conductive material layer formed on the surface of the silicon substrate is dissolved and thus ions derived from a metal element composing the conductive material (hereinafter, referred to as “derived ions”) are generated in the etchant.
During washing an etchant adheringed to a surface with water after a wet process, a small amount of adhering etchant is diluted, so that the level of the above-mentioned various trace ion species is further lowered. As a result, it is quite rare that various molecules or ion species:dissolved in the etchant remain on the surface. The substrate surface, therefore, usually becomes considerably clean after the wet process. In other words, in each process, a process design and conditions are chosen to substantially eliminate element ions or compound molecules inevitably contained in an etchant from the surface by removing the etchant with water after the process.
There will be described a wet process in a manufacturing process for a MOSFET for a logic circuit whose manufacturing process has been already established. For a series of steps for manufacturing an N-MOSFET for a logic circuit,
FIG. 6
shows the first half to the step of forming an FET while
FIG. 7
shows the latter half from the step of forming an interlayer insulating film. Purposes of wet processes in the manufacturing process and types of dopants used therein will be described with reference to cross sections sequentially shown in
FIGS. 6 and 7
according to the process order.
In the step illustrated in FIG.
6
(
a
), on a silicon substrate
601
is formed a buried oxide film for separation between devices. On the substrate surface is formed a trench by a known etching technique. On the substrate surface on which the trench has been formed is deposited an oxide film
600
by a known bias CVD technique. Then, as illustrated in FIG.
6
(
a
), the oxide film
600
is removed by a chemical-mechanical polishing (CMP) technique to expose the surface of the silicon substrate
601
. The oxide film buried in the trench becomes a shallow trench isolation (STI)
602
(hereinafter, referred to as a “trench isolation”) for separation between devices. In the above series of steps, the rear face of the wafer is cleaned after CMP for removing, e.g., an oxide film adhering to the rear face.
Subsequently, in the step illustrated in FIG.
6
(
b
), for example, B (boron) as an N-type dopant is ion-implanted with given depth and doping amount according to a designed threshold voltage of an FET to form a doping area
603
. After the step, the exposed silicon substrate
601
is covered with a natural oxide film formed during the step. The uneven natural oxide film is removed by dissolving and cleaning with an agent such, as diluted hydrofluoric acid (DHF; diluted HF). The exposed substrate surface is sequentially washed with an ammonium hydroxide-hydrogen peroxide mixture (APM), a hydrochloric acid-hydrogen peroxide mixture (HPM) or a sulfuric acid-hydrogen peroxide mixture (SPM), to remove contaminants adhering to the silicon substrate surface (the first cleaning step). Then, as illustrated in FIG.
6
(
b
), on the clean surface thus obtained is formed a gate insulating film
604
with a given thickness.
Then, in the step illustrated in FIG.
6
(
b
), on the gate insulating film
604
is deposited a polysilicon layer by CVD. Since the polysilicon layer is used as a gate, it is doped with, for example, an N-type dopant such as P (phosphorous) to a concentration of, e.g., about 10
20
cm
−3
for endowing desired conductivity. Then, a resist pattern
630
to be an etching mask is formed by a known photolithography. Using the mask, the polysilicon is selectively etched by reactive dry etching using a reactive gas such as HBr and Cl
2
, to form a gate electrode shape. As shown in FIG.
6
(
c
), the gate. insulating film
604
remains only under the gate electrode
605
while the insulating film
604
covering the other area is also removed.
The resist
630
is peeled off by SPM cleaning and then APM cleaning. The surface is cleaned with an ammonium hydroxide-hydrogen peroxide mixture (APM) and then HPM or SPM to remove contaminants and residual organic compounds on the polysilicon of the gate electrode
605
and the silicon surface in areas to be a source-drain area
606
,
607
(the second cleaning step). Then, for example, P (phosphorous) as an N-type dopant is ion-implanted at a low level, using the gate electrode
605
as an implanting mask to form light-doping areas
606
,
607
.
Then, in the step illustrated in FIG.
6
(
d
), an insulating film is deposited on the whole surface of the substrate including the polysilicon of the gate electrode
605
. The insulating film is etched by dry etching with perpendicular anisotropy, so that only the insulating film deposited on the side wall of the gate electrode
605
can remain to form a side wall
605
a
. Then, for example, As (arsenic) as an N-type dopant is ion-implanted at a high level using the gate electrode
605
and the side wall
605
a
covering its wall as an implanting mask to form heavy-doping areas
608
,
609
. In this step, as shown in FIG.
6
(
d
), there is formed a main part of a MOSFET with a self-aligned LDD structure.
Then,
Foley & Lardner
NEC Electronics Corporation
Von Buhr Maria N.
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