Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Reexamination Certificate
2002-02-07
2004-03-16
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
C257S622000, C438S110000, C438S113000, C438S458000, C438S460000, C438S462000, C438S912000
Reexamination Certificate
active
06707133
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor chip obtained by cutting, from a wafer, an element occupying a non-rectangular area. The present invention also relates to a module containing an element occupying a nonrectangular area. For example, the present invention relates to a chip and a manufacturing method thereof such as an arrayed waveguide grating chip, a manufacturing method thereof, and manufacturing a module containing an arrayed waveguide grating chip.
2. Description of the Related Art
As the volume of data to be transmitted increases, there is a corresponding demand for a larger transmission capacity in an optical fiber communications system. In addition, optical wavelength filtering is becoming increasingly important as an optical multiplexing/demultiplexing device for multiplexing and/or demultiplexing different wavelengths in Dense Wavelength Division Multiplexing (DWDM) systems. There are various types of optical wavelength filters. Among these, an arrayed waveguide grating has the desired wavelength characteristics such that a high extinction ratio is obtained in a narrow band region, and also features a filter device having multiple inputs and outputs. An arrayed waveguide grating is capable of multiplexing or demultiplexing signals, allowing a wavelength multiplexing/demultiplexing device can be easily constructed. Further, when the arrayed waveguide grating is constructed with quartz waveguides, the arrayed waveguide grating couples well with optical fibers and operates at small insertion loss, i.e., on the order of several dB (decibels). Due to these advantages, the arrayed waveguide grating is gaining recognition as a particularly important device among the optical wavelength filters.
FIG. 1
shows an overall structure of a related arrayed waveguide grating. An arrayed waveguide grating comprises one or plural input waveguides
12
formed on a substrate
11
, a plurality of output waveguides
13
, a channel waveguide array
14
wherein the respective arrayed waveguides are curved in a certain direction, each waveguide having a different curvatures. The arrayed waveguide grating further comprises an input side slab waveguide
15
for connecting the input waveguides
12
with the channel waveguide array
14
, and an output side slab waveguide
16
for connecting the channel waveguide array
14
with the output waveguides
13
. Multiplexed optical signals entering from the input waveguides
12
have their propagation paths expanded at the input side slab waveguide
15
before entering the channel waveguide array
14
. In the channel waveguide array
14
, the individual arrayed waveguides comprising the channel waveguide array
14
have mutually different optical path lengths. The individual arrayed waveguides are configured to progressively become either longer or shorter. Therefore, light propagating through the individual arrayed waveguides of the channel waveguide array
14
are imparted with predetermined phase differences before reaching the output side slab waveguide
16
. As a result, light is focused (condensed) at mutually different positions on the interface of the output side slab waveguide
16
and the output waveguides
13
depending on wavelength. Since the output waveguides
13
are arranged at positions corresponding to different wavelengths, any given wavelength component can be taken from one of the output waveguides
13
. Referring to
FIG. 2
, arrayed waveguide gratings
10
are commonly formed on a wafer comprising a silicon base or a quartz base. The wafer has a substantially disk-like shape, on which a plurality of the arrayed waveguide gratings
10
are formed and subsequently cut out into individual chips. For the cutting operation, it has been customary to use a technique called dicing, in which a saw blade is used to scan along predetermined cutting tracks.
FIG. 2
shows how arrayed waveguide gratings
10
are laid out on a wafer for related cutting operations. In
FIG. 2
, the arrayed waveguide gratings
10
are cut along the cutting paths
22
and
23
, respectively scribed in the X-axis and Y-axis directions at predetermined intervals, into individual chips, each having a rectangular shape.
As described above, it has been common cut a wafer using the cutting paths
22
and
23
to obtain individual chips of a rectangular shape. Cutting out individual rectangular shaped chips this way is efficient for ordinary integrated circuits, since the integrated circuit itself is formed into a rectangular shape.
The arrayed waveguide gratings shown in
FIG. 1
are formed in an arcuate or a boomerang-like shape. Consequently, when arrayed waveguide gratings are cut out as rectangular chips as in the related art, wafer utilization efficiency is low since there is wasted space. Referring to
FIG. 2
, when a wafer
21
having a diameter of about 13 cm is used, only about 4 to 6 chips of the arrayed waveguide gratings can be obtained from one wafer
21
. Thus, the arrayed waveguide gratings occupy a small area relative to the entire area of a wafer.
FIG. 3
shows an example of 1×N splitters as another layout on a wafer. In this example, 1×N splitter chips
33
are cut out from a wafer
21
by using cutting paths
31
and
32
. Although a 1×N splitter itself in this example is formed in a funnel shape obtained by dividing a rhombus in half, this is cut out in a rectangular shape, whereby only two chips
33
are cut out from one wafer
21
. Thus, there is a similar problem low wafer utilization efficiency.
SUMMARY OF THE INVENTION
In view of the above, it is therefore an aspect of the present invention to provide a method of cutting a chip from a wafer such that a greater number of chips can be obtained from one wafer. In an exemplary embodiment, arrayed waveguide gratings having a non-rectangular area as a whole are provided on a wafer and cut therefrom, and a module containing an arrayed waveguide grating is manufactured.
To solve the above problem, a chip of the present invention is obtained by cutting it from a wafer along its contour of a concave shape recessed in one direction. An arrayed waveguide grating is provided on the chip, and the shape of the chip is determined on the basis of the shape of the arrayed waveguide grating. The chip comprises reinforcement means mounted on at least a portion of the chip so as to reinforce the chip. It is preferable that the reinforcement means are mounted on a narrow part of the chip. The reinforcement means is preferably a copper plate having a shape identical to the chip. The reinforcement means may be a rectangular copper plate formed with such a size as to entirely surround the chip. Moreover, a chip of the present invention comprises a first chip obtained by cutting it from a first wafer along its contour of a concave shape recessed in one direction, a second chip obtained by cutting it from a second wafer along a contour that is identical to the contour of the first chip and combining means for combining the first chip with the second chip. The combining means can be an adhesive.
A wafer of the present invention includes a plurality of chips obtained by cutting along the contour of a concave shape recessed in one direction. The concave shapes of adjacent chips are at least partially overlapped with each other. The plurality of chips have the same shape. The shape is an arcuate shape having two curved-line portions convexed in the same direction. The chips are arranged at a predetermined spacing and respective end portions thereof are connected to two mutually parallel straight lines. Alternatively, the shape is a funnel shape obtained by dividing in half a rhombus in which two curved-line portions are convexed in a direction moving away from each other. The chips are arranged at a predetermined spacing and the respective end portions thereof are connected to two mutually parallel straight lines.
Another aspect of the present invention provides a module comprising a chip cut from a wafer along a contour of a concave shap
Katou Hiroyuki
Watanabe Shinya
Huynh Andy
Nelms David
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