Optics: measuring and testing – Inspection of flaws or impurities – Surface condition
Reexamination Certificate
2001-07-12
2004-04-13
Rosenberger, Richard A. (Department: 2877)
Optics: measuring and testing
Inspection of flaws or impurities
Surface condition
C438S016000, C324S1540PB, C356S239700
Reexamination Certificate
active
06721046
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to semiconductor processing, and in particular to systems and methods for monitoring and regulating the concentration of nitrogen in a nitrided gate oxide layer.
BACKGROUND OF THE INVENTION
In the semiconductor industry, there is a continuing trend toward manufacturing integrated circuits with a greater number of layers and with higher device densities. To achieve these high densities there have been, and continue to be, efforts towards reducing the thickness of layers, improving the uniformity of layers, reducing the thickness of devices and scaling down device dimensions (e.g., at sub micron levels) on semiconductor wafers. In order to accomplish higher device packing densities, thinner layers, more uniform layers, smaller feature sizes, and smaller separations between features are required. This can include the width and/or thickness of gate oxide materials, (e.g., silicon oxide, silicon nitride, silicon oxynitride, high K metal oxides), interconnecting lines, spacing and diameter of contact holes, and the surface geometry such as corners and edges of various features.
But as lateral device dimensions are scaled deeply into the sub-micron range, as required to achieve desired speed and integration improvements, corresponding reductions in gate-oxide thickness can have undesired impacts. For example, problems associated with direct tunneling can occur when gate oxide thickness decreases below certain thresholds. For example, as the gate oxide thickness is reduced into the sub-two nanometer region, a rapid increase in direct tunneling and boron penetration in PMOS devices can be a major obstacle for device scaling.
The process of manufacturing semiconductors, or integrated circuits (commonly called ICs, or chips), typically consists of more than a hundred steps, during which hundreds of copies of an integrated circuit can be formed on a single wafer. Generally, the process involves creating several layers on and/or in a substrate that ultimately forms the complete integrated circuit. This layering process can create electrically active regions in and/or on the semiconductor wafer surface. Insulation and conductivity between such electrically active regions can be important to reliable operation of such integrated circuits. Thus, controlling the width and/or uniformity of layers created during the layering process can be important to the reliable operation of such integrated circuits. Further, the insulating and/or conducting properties of a layer can be affected by the chemical composition of a layer (e.g., the concentration of one or more elements). One type of integrated circuit in which insulation and conductivity between electrically active regions is important is electronic memory.
Electronic memory comes in different forms to serve different purposes. One such electronic memory, flash memory can be employed for information storage in devices including, but not limited to, voice recorders, cellular phones, digital cameras and home video game consoles. Flash memory can be considered a solid-state storage device, in that functionality is achieved electronically rather than mechanically. Flash memory is a type of EEPROM (Electrically Erasable Programmable Read Only Memory) chip. Flash memories are a type of non-volatile memory (NVM). NVMs can retain information when power to the NVM is removed in contrast to NVMs with volatile memories (e.g., DRAM, SRAM) that lose stored data when power is removed. Flash memory is electrically erasable and re-programmable in-system. The combination of non-volatility and in-system eraseability/re-programmability make flash memory well-suited to a number of end-product applications including, but not limited to, personal computer BIOS, telecom switches, cellular phones, internetworking devices, instrumentation, automotive devices and consumer-oriented voice, image and data storage devices (e.g., digital cameras, digital voice recorders, PDAs).
An exemplary MOSFET
100
(Metal Oxide Semiconductor Field Effect Transistor), another semiconductor device, is illustrated in Prior Art. FIG.
1
. The exemplary MOSFET device
100
illustrated includes a gate
104
separated from a substrate
110
by a gate oxide
102
. The MOSFET includes a source
106
and a drain
108
. The components of the thin gate oxide
102
can be important to reliable operation of the MOSFET
100
, and thus, manufacturing the gate oxide
102
with desired components to precise measurements facilitates increasing MOSFET reliability.
The gate oxide layer
102
functions as an insulating layer. The gate oxide layer
102
can be the smallest feature of a device. Controlling the components of the gate oxide layer
102
can contribute to increasing the switching speed of a transistor. Thus, precisely monitoring and controlling properties of the gate oxide layer
102
including, but not limited to, relative material concentration, are important to facilitating reliable operation of the MOSFET
100
. For example, the ability to store data, to retain data, to be erased, to be reprogrammed and to operate in desired electrical and temperature ranges can be affected by the components that constitute the gate oxide layer
102
.
In deep submicron CMOS technology to improve the reliability of ultra-thin gate oxides and also to prevent boron penetration from the poly gate, different nitridation techniques are used to incorporate nitrogen into gate oxides. Nitridation can be done by in situ or post annealing of oxides in an ambient of nitric oxide (NO), nitrous oxide, or ammonia. Alternate techniques include implanting nitrogen into the gate oxides. The nitridation process can be done in batch type furnace or in a single wafer processing cluster tool. Stacked gate oxides are also prepared by depositing a thin nitride layer on an oxide. Plasma nitridation techniques such as RPN (remote plasma nitridation) and DPN (decoupled plasma nitridation) are also employed for nitridation.
The insulating properties of the gate oxide layer
102
can be affected not only by its thickness but by the chemical composition of the gate oxide layer
102
, including the concentration of nitrogen. Precisely controlling the gate oxide thickness and composition (such as nitrogen concentration) are required to maintain current levels required for circuit operation in devices employing a gate oxide layer
102
.
Properties of the gate oxide layer
102
including, but not limited to, chemical composition (e.g., nitrogen concentration), thickness and uniformity can affect the operation of one or more MOSFETs fabricated on the gate oxide layer
102
. It is to be appreciated that the present invention can be applied to the formation of gate oxide layers in other integrated circuits. For example, the present invention can be applied to all (for example in DRAM, SRAM, and other memory devices, microprocessors, logic circuits and tunnel oxides in EEPROM type flash memory devices and SONOS type flash memory devices) CMOS devices where thin nitrided gate oxides are used. The technique can also be applied to oxynitrides, or oxide
itride type stacked gate oxides.
The requirement of small features with close spacing between adjacent features in semiconductor devices with submicron geometry requires sophisticated manufacturing techniques including precise control of gate oxide layer formation. By way of illustration, fabricating microprocessor or memory devices using such sophisticated techniques may involve a series of steps including the formation of layers/structures by chemical vapor deposition (CVD), rapid thermal oxidation and oxide growth. Conventionally, difficulties in forming ultra thin gate oxide layers, with precise nitrogen concentration, have limited the effectiveness and/or reliability of such devices manufactured by conventional techniques. By way of further illustration, for CMOS devices, similar gate oxide considerations can apply to at least two different portions of a gate dielectric structure: the Si—SiO
2
interface and the bulk of dielectric film. The S
Halliyal Arvind
Singh Bhanwar
Subramanian Ramkumar
Advanced Micro Devices , Inc.
Amin & Turocy LLP
Barth Vincent P.
LandOfFree
Monitoring of concentration of nitrogen in nitrided gate... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Monitoring of concentration of nitrogen in nitrided gate..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Monitoring of concentration of nitrogen in nitrided gate... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3244694