Semiconductor memory device including magneto resistive...

Details Semiconductor memory device including magneto resistive... Semiconductor memory device including magneto resistive...

2003-07-09

2004-07-20

Nguyen, Cuong (Department: 2811)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C438S073000

Reexamination Certificate

active

06764865

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of fabricating the same and, more particularly, to an MRAM (Magnetic Random Access Memory) using a TMR (Tunneling Magneto Resistive) element as a memory element and a method of fabricating the same.
2. Description of the Related Art
Recently, an MRAM (Magnetic Random Access Memory) cell using the tunnel magneto resistive (to be referred to as TMR hereinafter) effect as a data memory element has been proposed.
FIG. 14
is a plan view of a semiconductor memory device according to prior art.
FIG. 15
is a sectional view of this semiconductor memory device taken along a line XV—XV in FIG.
14
.
FIG. 16
shows the magnetization state in a magnetic recording layer of the semiconductor memory device according to this prior art.
As shown in
FIGS. 14 and 15
, bit lines
11
and write word lines
13
are so formed as to cross each other at right angles. TMR elements
23
are formed at the intersections of the bit lines
11
and the write word lines
13
. One end of each TMR element
23
is connected to the bit line
11
, and the other end of the TMR element
23
is connected to a read word line
30
via a lower electrode
40
and a contact
41
.
The TMR element
23
has a three-layered structure including two magnetic layers and a nonmagnetic layer sandwiched between these magnetic layers. That is, the TMR element
23
is composed of a magnetic recording layer
24
which connects to the bit line
11
via an upper electrode (not shown), a magnetization fixing layer
25
which connects to the lower electrode
40
, and a thin tunnel insulating film
19
sandwiched between the magnetic recording layer
24
and the magnetization fixing layer
25
.
This semiconductor memory device according to the prior art has the following problems.
First, the magnetic recording layer
24
, the magnetization fixing layer
25
, and the tunnel insulating film
19
constructing the TMR element
23
are formed in a plane parallel to a semiconductor substrate (not shown) on which this TMR element is mounted. When the TMR element
23
is patterned, therefore, the surface area of this TMR element
23
depends upon the minimum dimension of lithography. That is, the degree of freedom of processing of the TMR element
23
is low.
Also, it is originally ideal in the magnetic recording layer
24
that all the magnetization directions point in the same direction. In practice, however, as shown in
FIG. 16
, a magnetic domain
100
in which the magnetization vectors in the longitudinal direction turn is generated in each of the two end portions of the magnetic recording layer
24
. This magnetic domain
100
generates a so-called demagnetizing field. Consequently, a region in which this demagnetizing field is generated can no longer uniformly maintain tunnel resistances corresponding to the original storage states of data “1” and “0”. This problem becomes conspicuous when the TMR element
23
is downsized. That is, to downsize the area component, which is parallel to the semiconductor substrate, of the TMR element
23
, the surface area of the TMR element
23
must be decreased. More specifically, as the surface area of the TMR element
23
decreases, the proportion of the magnetic field unstable region generated by the magnetic domain
100
in the end portion of the TMR element
23
increases. This makes it difficult to detect a difference in change amount between the tunnel resistances. Additionally, downsizing of the film thickness component, which is perpendicular to the semiconductor substrate, of the TMR element
23
is more difficult than downsizing of the area component of the TMR element
23
. Therefore, if downsizing of the area component of the TMR element
23
is advanced, a magnetic field required for switching increases, and this extremely increases an applied current when the magnetic field is generated. As described above, since downsizing of the TMR element
23
is difficult, downsizing of a cell is also difficult.
Furthermore, as shown in
FIG. 15
, the conventional cell requires one bit line
11
and two word lines (the write word line
13
and the read word line
30
) for each TMR element
23
. In addition, to connect the TMR element
23
to the read word line
30
, wiring must be extracted by using the lower electrode
40
, the contact
41
, and the like. Accordingly, the existence of various wiring and the like increases the minimum processing dimension of the cell to 8F
2
or more (FIG.
14
). This further makes downsizing of the cell difficult.
Also, as shown in
FIG. 15
, as a distance X′ between the write word line
13
and the TMR element
23
is shortened, the write current decreases, and this improves the operation margin. Hence, it is necessary to shorten this distance X′ between the write word line
13
and the TMR element
23
. However, it is very difficult in view of process to perform control such that a film thickness
16
a
of the insulating film between the write word line
13
and the TMR element
23
decreases.
As described above, in the semiconductor memory device according to the above prior art, the degree of freedom of the surface processing of the TMR element
23
is low, downsizing of the cell area is difficult, and control of the distance X′ between the write word line
13
and the TMR element
23
is difficult.
BRIEF SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a semiconductor memory device comprises a semiconductor substrate, and a first magneto resistive element separated from the semiconductor substrate, the first magneto resistive element comprising a first magnetic layer and a first nonmagnetic layer, the first magnetic layer and the first nonmagnetic layer being formed in a direction perpendicular to the semiconductor substrate.
According to a second aspect of the present invention, a method of fabricating a semiconductor memory device, comprises forming first wiring above a semiconductor substrate, forming a first insulating film on the first wiring, forming second and fourth wiring on the first insulting film, the fourth wiring being formed away from the second wiring with a first space therebetween, partially forming a second insulating film on the first insulating film and on the second and fourth wiring to form a first trench in the first space, forming first and second magneto resistive elements on two side surfaces of the first trench, the first magneto resistive element comprising a first magnetic layer and a first nonmagnetic layer, the first magnetic layer and the first nonmagnetic layer being formed in a direction perpendicular to the semiconductor substrate, the second magneto resistive element comprising a second magnetic layer and a second nonmagnetic layer, and the second magnetic layer and the second nonmagnetic layer being formed in the direction perpendicular to the semiconductor substrate, removing the first insulating film from a bottom surface of the first trench between the first and second magneto resistive elements to form a contact hole which exposes a portion of the first wiring, and removing a portion of the second insulating film which are positioned above the second and fourth wiring to form second and third trenches, forming a contact in the contact hole, the contact being connected to the first wiring and to the first and second magneto resistive elements, and forming third and sixth wiring in the second and third trenches, respectively, the third wiring being connected to the first magneto resistive element, and the sixth wiring being connected to the second magneto resistive element.


REFERENCES:
patent: 5835314 (1998-11-01), Moodera et al.
patent: 6509621 (2003-01-01), Nakao
patent: 6515341 (2003-02-01), Engel et al.

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