Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2001-09-06
2004-01-27
Cunningham, Terry D. (Department: 2816)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C327S563000
Reexamination Certificate
active
06683497
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a MOS differential amplifier circuit having linear transconductance formed on a semiconductor integrated circuit, and in particular, to a MOS linear transconductance amplifier that operates in a low voltage and is excellent in a frequency characteristic.
2. Description of the Prior Art
FIG. 8
is a circuit diagram showing a conventional MOS linear transconductance amplifier disclosed in Japanese Patent Laid-Open No. 11-251848.
This MOS linear transconductance amplifier comprises a MOS differential pair
1
formed with two n-channel MOS transistors M
1
and M
2
whose sources are connected with each other, and two n-channel MOS transistors M
3
and M
4
which operate as their load.
Sources of the MOS transistors M
1
and M
2
that form the MOS differential pair
1
are grounded through a constant current source
2
(current value: I
ss
). This MOS differential pair
1
is driven by the constant current I
ss
generated by the constant current source
2
. Gates of the MOS transistors M
1
and M
2
form an input terminal pair of the amplifier concerned, and an input voltage V
i
is applied between those gates. Each ratio (W/L) of gate width (W) and gate length (L) of the MOS transistors M
1
and M
2
is K
1
as large as that of a unit MOS transistor (K
1
is a constant, but K
1
≧1).
The MOS transistor M
3
operates as the load of the MOS transistor M
1
. A source of the MOS transistor M
3
is connected to a drain of the MOS transistor M
1
, and the drain of the MOS transistor M
3
is connected to a supply voltage line from which supply voltage V
DD
is applied, and a bias voltage (DC constant voltage) V
B
is applied to a gate of the MOS transistor M
3
.
The MOS transistor M
4
operates as the load of the MOS transistor M
2
. A source of the MOS transistor M
4
is connected to a drain of the MOS transistor M
2
, a drain of the MOS transistor M
4
is connected to the supply voltage line from which the supply voltage V
DD
is applied, and the same bias voltage V
B
as that applied to the MOS transistor M
3
is applied to a gate of the MOS transistor M
4
. Each ratio (W/L) of gate width (W) and gate length (L) of the MOS transistors M
3
and M
4
is K
2
as large as that of the unit MOS transistor (K
2
is a constant, however K
2
≧1).
Next, the operation principle of a MOS linear transconductance amplifier shown in
FIG. 8
will be described.
It is assumed that a body effect and a channel length modulation are disregarded and the relation between a drain current I
D
and a voltage between the gate and source of a MOS transistor which is operating in a saturation region follows a square-law. Then, the drain current I
D
is expressed as shown in a following formulas (1a) and (1b):
{
I
D
=
K
β
(
V
GS
-
V
TH
)
2
(
V
GS
≥
V
TH
)
I
D
=
0
(
V
GS
≤
V
TH
)
(1a)
(1a)
In these formulas (1a) and (1b), a symbol K is a ratio of the ratio (W/L) of the gate width (W) and gate length (L) of the MOS transistor to that of the unit MOS transistor. In addition, a symbol &bgr; is a transconductance parameter and a symbol V
TH
is threshold voltage. Assuming that an effective mobility of a carrier is &mgr; and a gate oxide film capacity per unit area is C
OX
, the transconductance parameter &bgr; will be defined by &bgr;=&mgr; (C
OX
/2) (W/L).
If it is assumed that characteristics of elements are almost consistent with each other, the two output currents I
D1
and I
D2
of the MOS differential pair
1
, i.e., the drain currents of these MOS transistors M
1
and M
2
, are expressed as shown in the following formulas (2a) and (2b), respectively.
I
D1
=
1
2
{
I
0
+
K
1
β
V
i
2
I
ss
K
1
β
-
V
i
2
}
(
&LeftBracketingBar;
V
i
&RightBracketingBar;
≤
I
ss
K
1
β
)
(2a)
I
D2
=
1
2
{
I
0
-
K
1
β
V
i
2
I
ss
K
1
β
-
V
i
2
}
(
&LeftBracketingBar;
V
i
&RightBracketingBar;
≤
I
ss
K
1
β
)
(2b)
As shown in formulas (2a) and (2b), an operational input voltage range of the MOS differential pair
1
is |V
i
|≦{I
ss
/(K
1
&bgr;)}.
The drain currents I
D1
and I
D2
of the MOS transistors M
1
and M
2
expressed in formulas (2a) and (2b) are converted into voltages respectively by square root (root) compression performed by the MOS transistors M
3
and M
4
serving as their loads. Therefore, two output voltages V
01
and V
02
of the MOS differential pair
1
having the MOS transistors M
3
and M
4
as loads are generated in the drains of the MOS transistors M
1
and M
2
respectively, and are expressed in the following formulas (3a) and (3b).
V
D1
=
V
B
-
V
TH
-
I
D1
K
2
β
(
&LeftBracketingBar;
V
i
&RightBracketingBar;
≤
I
ss
K
1
β
)
(3a)
V
D2
=
V
B
-
V
TH
-
I
D2
K
2
β
(
&LeftBracketingBar;
V
i
&RightBracketingBar;
≤
I
ss
K
1
β
)
(3b)
That is, when a differential output voltage of the MOS differential pair
1
is defined as &Dgr;V, the &Dgr;V is expressed as follows.
Δ
V
=
V
O1
-
V
O2
=
-
1
K
2
β
(
I
D1
-
I
D2
)
(
4
)
Here, a following formula (5) is introduced. In the formula (5), symbols a and b are constants and symbol x is a variable.
b
(
a
+
2
x
1
-
x
2
2
-
a
-
2
x
1
-
x
2
2
)
=
b
2
x
(
5
)
In addition, in the formula (5), these symbols a, b, and x are set up as follows.
a
=
1
,
b
=
I
ss
/
2
,
x
=
V
i
/
I
SS
K
1
β
(
6
)
Then, the left side of the formula (5) becomes equal to what is obtained by substituting the formulas (2a) and (2b) for the formula (4). At this time, the right-hand side of the formula (5) becomes (K
1
&bgr;)·V
I
. Therefore, the following formula (7) is obtained.
Δ
V
=
1
K
2
β
(
I
D1
-
I
D2
)
=
1
K
2
β
K
1
β
V
i
(
&LeftBracketingBar;
V
i
&RightBracketingBar;
≤
I
SS
K
1
β
)
(
7
)
It is obvious from
FIG. 7
, the differential output voltage &Dgr;V of the MOS differential pair
1
, i.e., a difference between the square roots of the drain current I
D1
and drain current I
D2
expressed by the formulas (2a) and (2b), respectively, is proportional to an input voltage V
i
as apparent from this formula (7).
In addition, when a differential output current of the MOS differential pair
1
is defined as &Dgr;I
D
, &Dgr;I
D
is expressed like a following formula (8) with using drain currents I
D1
and I
D2
.
Δ
I
D
=
I
D1
-
I
D2
=
(
I
D1
-
I
D2
)
(
I
D1
+
I
D2
)
=
K
1
β
V
i
2
I
SS
K
1
β
-
V
i
2
(
&LeftBracketingBar;
V
i
&RightBracketingBar;
≤
I
SS
K
1
β
)
(
8
)
Therefore, it can be seen that the differential output current &Dgr;I
D
of the MOS differential pair
1
includes a linear term shown in formula (9) and a nonlinear term shown in formula (10) as follows:
I
D1
-
I
D2
=
K
1
β
V
i
(
&LeftBracketingBar;
V
i
&RightBracketingBar;
≤
I
SS
K
1
β
)
(
9
)
I
D1
+
I
D2
=
K
1
β
2
I
SS
K
1
β
-
V
i
2
(
&LeftBracketingBar;
V
i
&RightBracketingBar;
≤
I
SS
K
1
β
)
(
10
)
Letting the source voltage of the MOS transistors M
1
and M
2
, which form the MOS differential pair
1
and whose sources are mutually connected, be a common source voltage V
S1
, the common source voltage V
S1
is expressed in the following formula (11).
V
S1
=
V
CM1
-
V
TH
-
1
2
2
I
SS
K
1
β
-
V
i
2
(
11
)
In the formula (11), V
CM1
is a common mode voltage of the input voltage V
i
that is differentially inputted. As shown in the formula (11), since the common source voltage V
S1
is a function of the input voltage V
i
, the common source voltage V
S1
is changed with an input voltage V
i
. Moreover, a 3rd term (square root term) in the formula
Cunningham Terry D.
McGinn & Gibb PLLC
Tra Quan
LandOfFree
MOS linear transconductance amplifier does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with MOS linear transconductance amplifier, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MOS linear transconductance amplifier will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3243448