Electrical connectors – Preformed panel circuit arrangement – e.g. – pcb – icm – dip,... – With provision to conduct electricity from panel circuit to...
Reexamination Certificate
2002-11-13
2004-07-27
Nasri, Javaid H. (Department: 2839)
Electrical connectors
Preformed panel circuit arrangement, e.g., pcb, icm, dip,...
With provision to conduct electricity from panel circuit to...
C324S754090
Reexamination Certificate
active
06767219
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a contactor, in particular to a contactor contacting a terminal of a subject to be tested such as a semiconductor substrate (wafer), a wiring substrate, and an electrical component for performing electrical testing, a method for manufacturing such contactor, a method for contacting the wiring substrate using such contactor, and a testing method.
2. Description of the Related Art
Recently, with respect to semiconductor devices represented by an LSI (the semiconductor device is referred to as an LSI hereinafter), in order to accommodate the demands for down-sizing of a product to which the LSI is applied or for multi-functionalization of the product in case the size is the same as a conventional product, the wiring is increasingly arranged in more detail and also the circuit density is increasing. The finer arrangement of the wiring and the increase in the circuit density are accompanied by the increase in the number of terminals and the miniaturization of the terminals. Accordingly, the miniaturization of the contact electrode and the increase in the number of contact electrodes provided on the contactor (probe card) for testing the LSI in a wafer form are also demanded.
Previously, the LSI was usually tested and shipped in a packaged state but in recent years, more LSIs are tested and shipped in so called Known-Good-Die (KGD) state in which the LSI is tested in chip or wafer state without being packaged. The main reason for the sudden increase in the KGD is the increase 1) in the type of usage of so-called “bear chip packaging” in which the semiconductor chip is directly mounted to the substrate of the apparatus without being packaged (for downsizing) and 2) in the type of usage of so-called Multi Chip Module (MCM), or Multi Chip Package (MCP) or System In Package (SIP) in which a plurality of semiconductor chips is incorporated in a single package (for even more downsizing and multi-functionalizing).
In the manufacturing process of a semiconductor device for the type of usage as mentioned above, the testing items implemented in the conventional packaged state need to be implemented in the wafer or chip state. The terminal pitch of the wafer (chip) (mainly under 100 micrometers) with respect to the terminal pitch of the package (mainly 0.5 to 1.27 millimeters) is minute and the terminal size is also accordingly minute. Obviously, the performance of the testing contactor for the wafer is more demanding than that for the packaging.
Further, not only a peripheral terminal, which is predominantly manufactured conventionally, but also the number of manufactured area array terminals is increasing. The peripheral terminal is a pad terminal with an aluminum surface provided about the periphery of the chip for wiring the chip with a wire bond. The area array terminal is a terminal arranged in a grid shape on the chip area and a solder bump is mainly used as terminal material.
For a conventional peripheral terminal, a contact probe with an electrode contacting only the pad terminal arranged on the periphery of the semiconductor device is used. However, for the area array terminal, a contact probe having the ability to contact any position in the chip dimension is necessary.
Testing the LST in a discrete chip or in a packaged state is referred to as “a discrete testing”, whereas testing the LSI in the wafer state before cutting out into small pieces of LSI is referred to as “wafer level testing.” The wafer level testing tests the LSI after the wafer process and before the packaging, however, it includes the LSI applied with an additional process after the wafer process, such as the wafer level CSP packaged in the wafer state.
Also, the wafer which has been diced (cut) but still maintains the arrangement prior-to-cutting, due to being loaded on the dicing tape on which each chip is fixed and supported, may be considered to be included in the wafer level testing.
Since the wafer level testing allows the performance of testing without cutting the semiconductor wafer into the chips, the handling efficiency can be improved. Also, even when the size of the chip varies, since the wafer profile is fixed and standardized, testing equipment implementing the wafer level testing has a higher versatility than those implementing the discrete testing.
For the contactor (probe) for the wafer level testing, the following characteristics are required:
A) miniaturization of the terminal: A plurality of contact electrodes enabled to contact minute terminals arranged in narrow intervals is needed.
B) arrangement freedom: The plurality of contact electrodes can be arranged freely. In other words, the contact electrodes may be arranged not only around the periphery area but also as an array (grid). When all contact electrodes are arranged within the chip dimension, the chips adjacent to one another can be tested simultaneously.
C) widening of the contact area: Contact electrodes enabled to contact a plurality of LSIs at a time are required.
D) depressurization: Lessening the force applied to the thinner wafers, for example reducing the contact collective force, which is the summation of contact pressure of each contact electrode, with respect to the increase in the number of simultaneous testing or to increasing the number of pins of the LSI. For example, when the contact pressure of one pin is 10 g, the collective force for 50,000 terminals would add up to 5,000 kg.
E) cost reduction: The life cycle of the LSI wafer itself is becoming shorter. For example, in the case of general-purpose memory, the miniaturization of chips is performed approximately every 6 months and the terminal arrangement on the wafer is also changed. Also, more so-called ASICs specialized for particular customers and products are manufactured among the LOGIC products, and in particular, those for portable device applications have shorter life cycles. In view of the above, for the contactor (probe card) provided for each LSI wafer, the durability is important but also the contactor needs to be provided at a cost that pays off during a limited period of service.
With respect to the above-mentioned requirements, the prior art and the problems related thereto are listed below.
(I) Needle Method
1) Cantilever Method:
In this method, the needle point of a needle is registered with a terminal on the wafer and the other end of the needle is connected to the substrate. The interval of the terminals on the substrate side is larger than that of the terminals on the wafer side. Thus, the cantilever method has a constraint in terms of the terminal arrangement due to the configuration and therefore cannot address the requirement B) mentioned above. Also, this method has a constraint with respect to the requirement C). Therefore, since the terminals cannot be arranged as an area array or the dimension of the probe is larger than that of the chip, there exists a problem that the neighboring chips cannot be contacted simultaneously.
2) Vertical Probe Method:
2-1) Spring Probe (POGO-PIN) Method
With respect to the requirement A), the narrow pitch is structurally limited. In other words, the reduction of winding diameter of the coil spring has a limit. Also, with respect to the requirement D), in the depressurized state, stable contact cannot be obtained since there is no wiping motion so as to break the oxide film of the LSI terminals. Further, with respect to the requirement E), there exists a problem in that the spring probe is expensive due to the structural factors. In other words, it is necessary to wind the coil having a minute diameter separately. Also, a separate high precision boring component is necessary so as to maintain the position precision of the needle point.
2-2) Vertical Needle:
A conductive needle (rod-like member) rising in the vertical direction is set as a contact electrode. With respect to the requirement A), the displacement is caused by buckling and the direction in which the needle will bend cannot be determined in advance. Therefor
Fujisawa Tetsuya
Igawa Osamu
Kohashi Naohito
Maruyama Shigeyuki
Tashiro Kazuhiro
Armstrong Kratz Quintos Hanson & Brooks, LLP
Fujitsu Limited
Nasri Javaid H.
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