Synchronous clock generator including a false lock detector

Details Synchronous clock generator including a false lock detector Synchronous clock generator including a false lock detector

1997-08-29

1999-08-17

Heckler, Thomas M.

G06F 104

Patent

active

059406097

ABSTRACT:
A false lock detector for use in conjunction with a locked loop which produces a plurality of output signals in response to a clock signal is comprised of a logic circuit for receiving first and second signals produced by the locked loop. The logic circuit determines if a predetermined phase relationship exists between the first and second signals and produces an output signal indicative of that determination.

REFERENCES:
patent: 4077016 (1978-02-01), Sanders et al.
patent: 4687951 (1987-08-01), McElroy
patent: 4773085 (1988-09-01), Cordell
patent: 4893087 (1990-01-01), Davis
patent: 4902986 (1990-02-01), Lesmeister
patent: 5020023 (1991-05-01), Smith
patent: 5038115 (1991-08-01), Myers et al.
patent: 5087828 (1992-02-01), Sato et al.
patent: 5256989 (1993-10-01), Parker et al.
patent: 5257294 (1993-10-01), Pinto et al.
patent: 5268639 (1993-12-01), Gasbarro et al.
patent: 5283631 (1994-02-01), Koerner et al.
patent: 5295164 (1994-03-01), Yamamura
patent: 5337285 (1994-08-01), Ware et al.
patent: 5390308 (1995-02-01), Ware et al.
patent: 5408640 (1995-04-01), MacIntyre et al.
patent: 5420544 (1995-05-01), Ishibashi
patent: 5428311 (1995-06-01), McClure
patent: 5430676 (1995-07-01), Ware et al.
patent: 5440514 (1995-08-01), Flannagan et al.
patent: 5446696 (1995-08-01), Ware et al.
patent: 5448193 (1995-09-01), Baumert et al.
patent: 5473274 (1995-12-01), Reilly et al.
patent: 5473639 (1995-12-01), Lee et al.
patent: 5539345 (1996-07-01), Hawkins
patent: 5552727 (1996-09-01), Nakao
patent: 5572557 (1996-11-01), Aoki
patent: 5577236 (1996-11-01), Johnson et al.
patent: 5578940 (1996-11-01), Dillon et al.
patent: 5614855 (1997-03-01), Lee et al.
patent: 5657481 (1997-08-01), Farmwald et al.
patent: 5692165 (1997-11-01), Jeddeloh et al.
patent: 5712580 (1998-01-01), Baumgartner et al.
patent: 5751665 (1998-05-01), Tanoi
Alvarez, J. et al. "A Wide-Bandwidth Low Voltage PLL for PowerPC.TM. Microprocessors" IEEE IEICE Trans. Electron., vol. E-78, No. 6, Jun. 1995, pp. 631-639.
Arai, Y. et al., "A CMOS Four Channel x 1K Time Memory LSI with 1-ns/b Resolution", IEEE Journal of Solid-State Circuits, vol. 27, No. 3,M, 8107 Mar., 1992, No.3, New York, US.
Arai, Y. et al., "A Time Digitizer CMOS Gate-Array with a 250 ps Time Resolution", XP 000597207, IEEE Journal of Solid-State Circuits, vol. 31, No.2, February 1996.
Aviram, A. et al., "Obtaining High Speed Printing on Thermal Sensitive Special Paper with a Resistive Ribbon Print Head", IBM Technical Disclosure Bulletin, vol. 27, No. 5, Oct. 1984, pp. 3059-3060.
Bazes, M., "Two Novel Fully Complementary Self-Biased CMOS Differential Amplifiers", IEEE Journal of Solid-State Circuits, vol. 26, No. 2, Feb. 1991, pp. 165-168.
Cho, J. "Digitally-Controlled PLL with Pulse Width Detection Mechanism for Error Correction", ISSCC 1997, Paper No. SA 20.3, pp. 334-335.
Christiansen, J., "An Integrated High Resolution CMOS Timing Generator Based on an Array of Delay Locked Loops", IEEE Journal of Solid-State Circuits, vol. 31, No. 7, Jul. 1996, pp. 952-957.
Combes, M. et al., "A Portable Clock Multiplier Generator Using Digital CMOS Standard Cells", IEEE Journal of Solid-State Circuits, vol. 31, No. 7, Jul. 1996, pp. 958-965.
Descriptive literature entitled, "400MHz SLDRAM, 4M X 16 SLDRAM Pipelined, Eight Bank, 2.5 V Operation," SLDRAM Consortium Advance Sheet, published throughout the United States, pp. 1-22.
Donnelly, K. et al., "A 660 MB/s Interface Megacell Portable Circuit in 0.3 .mu.m-0.7 .mu.m CMOS ASIC", IEEE Journal of Solid-State Circuits, vol. 31, No. 12, Dec. 1996, pp. 1995-2001.
"Draft Standard for High-Speed Memory Interface (SyncLink)", Microprocessor and Microcomputer Standards Subcommittee of the IEEE Computer Society, Copyright 1996 by the Institute of Electrical and Electronics Engineers, Inc., New York, NY, pp. 1-56.
Goto, J. et al., "A PLL-Based Programmable Clock Generator with 50- to 350-MHz Oscillating Range for Video Signal Processors", IEICE Trans. Electron., vol. E77-C, No. 12, Dec. 1994, pp. 1951-1956.
Ishibashi, A. et al., "High-Speed Clock Distribution Architecture Employing PLL for 0.6 .mu.m CMOS SOG", IEEE Custom Integrated Circuits Conference, 1992, pp. 27.6.1-27.6.4.
Kim, B. et al., "A 30MHz High-Speed Analog/Digital PLL in 2 .mu.m CMOS", ISSCC, Feb. 1990.
Kikuchi, S. et al., "A Gate-Array-Based 666MHz VLSI Test System", IEEE Internation Test Conference, Paper 21.1, 1995, pp. 451-458.
Ko, U. et al., "A 30-ps Jitter, 3.6-.mu.s Locking, 3.3-Volt Digital PLL for CMOS Gate Arrays", IEEE Custom Integrated Circuits Conference, 1993, pp. 23.3.1-23.3.4.
Lee, T. et al., "A 2.5V Delay-Locked Loop for 18 Mb 500MB/s DRAM", IEEE International Solid-State Circuits Conference Digest of Technical Papers, Paper No. FA 18.6, 1994, pp. 300-301.
Lesmeister, G., "A Densely Integrated High Performance CMOS Tester", International Test Conference, Paper 16.2, 1991, pp. 426-429.
Nakamura, M. et al., "A 156 Mbps CMOS Clock Recovery Circuit for Burst-mode Transmission", Symposium on VLSI Circuits Digest of Technical Papers, 1996, pp. 122-123.
Nielson, E., "Inverting latches make simple VCO", EDN, Jun. 19, 1997.
Novof, I. et al., "Fully Integrated CMOS Phase-Locked Loop with 15 to 240 MHz Locking Range and .+-.50 ps Jitter", IEEE Journal of Solid-State Circuits, vol. 30, No. 11, Nov. 1995, pp. 1259-1266.
Santos, D. et al., "A CMOS Delay Locked Loop And Sub-Nanosecond Time-to-Digital Converter Chip", IEEE Nuclear Science Symposium and Medical Imaging Conference Record, vol. 1, Oct. 1995, pp. 289-291.
Saeki, T. et al., "A 2.5-ns Clock Access, 250-MHz, 256-Mb SDRAM with Synchronous Mirror Delay", IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1656-1665.
Shirotori, T. et al., "PLL-based, Impedance Controlled Output Buffer", 1991 Symposium on VLSI Circuits Digest of Technical Papers, pp. 49-50.
Sidiropoulos, S. et al., "A 700-Mb/s/pin CMOS Signaling Interface Using Current Integrating Receivers", IEEE Journal of Solid-State Circuits, vol. 32, No. 5, May 1997, pp. 681-690.
Sidiropoulos, S. et al., "A CMOS 500 Mbps/pin synchronous point to point link interface", IEEE Symposium on VLSI Circuits Digest of Technical Papers, 1994, pp. 43-44.
Sidiropoulos, S. et al., "A Semi-Digital DLL with Unlimited Phase Shift Capability and 0.08-400MHz Operating Range", in 1997 IEEE International Solid State Circuits Conference, Feb. 8, 1997, pp. 332-333.
Soyuer, M. et al., "A Fully Monolithic 1.25 GHz CMOS Frequency Synthesizer", IEEE Symposium on VLSI Circuits Digest of Technical Papers, 1994, pp. 127-128.
Tanoi, S. et al., "A 250-622 MHz Deskew and Jitter-Suppressed Clock Buffer Using a Frequency- and Delay-Locked Two-Loop Architecture", 1995 Symposium on VLSI Circuits Digest of Technical Papers, vol. 11, No. 2, pp. 85-86.
Tanoi, S. et. al., "A 250-622 MHz Deskew and Jitter-Suppressed Clock Buffer Using Two-Loop Architecture", IEEE IEICE Trans. Electron., vol.E-79-C. No. 7, Jul. 1996, pp. 898-904.
von Kaenel, V. et al., "A 320 MHz, 1.5 mW @ V CMOS PLL for Microprocessor Clock Generation", IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1715-1722.
Watson, R. et al., "Clock Buffer Chip with Absolute Delay Regulation Over Process and Environmental Variations", IEEE Custom Integrated Circuits Conference, 1992, pp. 25.2.1-25.2.5.
Yoshimura, T. et al. "A 622-Mb/s Bit/Frame Synchronizer for High-Speed Backplane Data Communication", IEEE Journal of Solid-State Circuits, vol. 31, No. 7, Jul. 1996, pp. 1063-1066.
Maneatis, Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques, Nov., 1996, IEEE Journal of Solid-State Circuits, vol. 31, Nov. 11, pp. 1723-1732.

Affiliated with

Also associated with

Rating

Synchronous clock generator including a false lock detector does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Synchronous clock generator including a false lock detector, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronous clock generator including a false lock detector will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-324074