Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2003-07-18
2004-09-21
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S172000, C327S336000, C327S554000
Reexamination Certificate
active
06795006
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrator circuits, and more particularly to reset mechanisms for differential integrator circuits.
2. Description of the Related Art
Integrator circuits are widely used in electronic circuits for a multitude of applications. In some applications, the integrators are part of a loop that can become unstable and need to be reset so that the circuit can function normally again. For example, delta-sigma modulators are commonly used in oversampling analog to digital (A/D) converters, where the delta-sigma modulator is typically of a high order and comprises a plurality of integration stages as illustrated in FIG.
1
. Some conditionally stable single loop high order delta-sigma modulators need to be reset when an unstable condition occurs, where the state variables of the modulator need to be reset to values within a stable state, such as zero, by resetting the integrators in the modulator.
The conventional method of resetting an integrator is illustrated in FIG.
2
. The integration circuit of
FIG. 2
comprises a differential operational amplifier (op-amp) having inverting and non-inverting inputs and inverting and non-inverting outputs. A first integration capacitor is coupled between the inverting input and non-inverting output, and a second integration capacitor is coupled between the non-inverting input and the inverting output. The integration circuit also includes a first reset switch coupled in parallel to the first integration capacitor, and a second reset switch coupled in parallel with the second integration capacitor. In operation of the integration circuit of
FIG. 2
, the integrator is reset to a stable state by closing the first and second reset switches, thereby short-circuiting the first and second integration capacitors.
The conventional method of resetting integrators, as illustrated in
FIG. 2
, however, has many disadvantages. For example, upon completion of a reset operation the common mode voltage of the input state is the same as the common mode voltage of the output stage. For some op-amp topologies, the input common mode voltage of the op-amp is designed to be different than the output common mode voltage for the op-amp to operate properly. For such an op-amp structure, additional cycles of operation of the integrator may be required after reset for the input common mode voltage to attain a value for proper operation.
Thus, additional methods and circuit implementations for resetting integrator circuits are needed in the technology.
SUMMARY OF THE INVENTION
In one aspect of the invention, an integrator circuit with a reset mechanism comprises an integration capacitor, a reset capacitor, a first integration switch coupled between an input of the integrator and an input side of the integration capacitor, a second integration switch coupled between an output side of the integration capacitor and an output of the integrator, a third integration switch coupled between an input common mode voltage and an input side of the reset capacitor, and a fourth integration switch coupled between an output side of the reset capacitor and an output common mode voltage. The integrator circuit further comprises a first reset switch coupled between the input of the integrator and the input side of the reset capacitor, a second reset switch coupled between the output side of the reset capacitor and the output of the integrator, a third reset switch coupled between the input common mode voltage and the input side of the integration capacitor, and a fourth reset switch coupled between the output side of the integration capacitor and the output common mode voltage, wherein the integration switches are closed during an integration mode and open during a reset mode, and wherein the reset switches are closed during the reset mode and open during the integration mode.
In another aspect of the invention, an integrator with a reset mechanism comprises a replacement integration capacitor which replaces an integration capacitor during a reset mode of the integrator. In a further aspect of the invention, the integration capacitor is charged to a predefined voltage during the reset mode.
In an additional aspect of the invention, a method of resetting an integrator comprises temporarily removing an integration capacitor and replacing the integration capacitor with a reset capacitor during a reset operation of the integrator. The method can further comprise charging the integration capacitor to a predefined voltage during the reset operation. In a further aspect of the invention, temporarily removing the integration capacitor and replacing the integration capacitor with the reset capacitor is repeated one or more times.
Another aspect of the invention is a delta-sigma modulator having a plurality of integration stages, wherein at least one of the integration stages comprises a first capacitor for integration and a second capacitor to replace the first capacitor in resetting the at least one integration stage.
In yet another aspect of the invention, a differential integrator comprises a pair of normal integration capacitors and a pair of reset integration capacitors, wherein the normal integration capacitors are rotated out of the integrator and the reset integration capacitors are rotated into the integrator to reset the integrator.
In an additional aspect of the invention, a circuit for resetting a state variable output of an integrator comprises a plurality of integration switches, wherein the integrator operates in a normal mode when the plurality of integration switches are closed, a plurality of reset switches, wherein the plurality of reset switches are open when the plurality of integration switches are closed, and at least one reset capacitor, wherein the reset capacitor replaces an integration capacitor between an input and an output of the integrator when the plurality of reset switches are closed and the plurality of integration switches are open.
An additional aspect of the invention is a digital microphone, comprising a circuit for resetting a state variable output of at least one integrator, wherein the at least one integrator comprises a first capacitor for integration and a second capacitor to replace the first capacitor in resetting the at least one integrator.
Yet another aspect of the invention is a microphone, comprising a transducer, a delta-sigma modulator coupled to the transducer, and means for maintaining the delta-sigma modulator in a stable state. The means for maintaining the delta-sigma modulator in a stable state can comprise a circuit for resetting a state variable output of an integrator of the delta-sigma modulator, comprising a plurality of integration switches, wherein the integrator operates in a normal mode when the plurality of integration switches are closed, a plurality of reset switches, wherein the plurality of reset switches are open when the plurality of integration switches are closed, and at least one reset capacitor, wherein the reset capacitor replaces an integration capacitor between an input and an output of the integrator when the plurality of reset switches are closed and the plurality of integration switches are open. The means for maintaining the delta-sigma modulator in a stable state can further comprise a limiter, coupled between the transducer and the delta-sigma modulator.
REFERENCES:
patent: 6061009 (2000-05-01), Krone et al.
patent: 6194946 (2001-02-01), Fowers
patent: 6362763 (2002-03-01), Wang
patent: 6661283 (2003-12-01), Lee
patent: 2002/0135402 (2002-09-01), Miyabe et al.
Delight Guy
LeReverend Remi
Knobbe Martens Olson & Bear LLP
Williams Howard L.
Zarlink Semiconductor AB
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