Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
Reexamination Certificate
2000-06-22
2004-04-20
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Reexamination Certificate
active
06725358
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to data processing and, in particular, to processing load-reserve and store-conditional instructions within a processor. Still more particularly, the present invention relates to an out-of-order execution processor that simplifies the use of reservations by validating reservations by reference to a load reorder queue.
2. Description of the Related Art
In shared memory multiprocessor (MP) data processing systems, each of the multiple processors in the system may access and modify data stored in the shared memory. In order to synchronize access to a particular granule (e.g., cache line) of memory between multiple processors, load-reserve and store-conditional instructions are often employed. For example, load-reserve and store-conditional instructions have been implemented in the PowerPC™ user instruction set architecture (UISA) with opcodes associated with the LWARX and STWCX mnemonics, respectively.
In typical shared memory MP data processing systems that support load-reserve and store-conditional instructions, each processor within the system is equipped with a special-purpose reservation register. When a processor executes a load-reserve to a memory granule, the processor loads some or all of the contents of the memory granule into one of the processor's internal registers and the address of the memory granule into the processor's reservation register. The requesting processor is then said to have a reservation with respect to the memory granule. The processor may then perform an atomic update to the reserved memory granule utilizing a store-conditional instruction.
When a processor executes a store-conditional to a memory granule for which the processor holds a reservation, the processor stores the contents of a designated register to the memory granule and then clears the reservation. If the processor does not have a reservation for the memory granule, the store-conditional instruction fails, and the memory update is not performed. In either case, a condition register bit is set to indicate whether or not the store-conditional was successful. In general, the processor's reservation is cleared if a remote processor requests exclusive access to the memory granule for purposes of modifying it (the request is made visible to all processors on the shared bus) or the reserving processor executes a store instruction targeting the reserved memory granule. If only one reservation is permitted per processor, a processor's current reservation will also be cleared if the processor executes another load-reserve instruction.
The present invention recognizes that reservation management as described above has traditionally been handled by a special-purpose reservation register and associated register management logic. The use of this special-purpose structure complicates processor design, data flow, and verification. Accordingly, the present invention provides an improved processor and method for handling reservations that simplifies processor design, data flow, and verification.
SUMMARY OF THE INVENTION
In accordance with the present invention, a processor includes a register set, at least one execution unit that executes load instructions to transfer data into the register set, a load queue and associated queue management logic. The load queue contains a plurality of entries that each include a reservation valid field, and each of the plurality of entries is associated with a respective one of a corresponding plurality of load instructions that includes at least one load-reserve instruction. In response to execution of the load-reserve instruction, the queue management logic detects whether a data hazard exists by reference to the load queue, and if so, initiates correction of the data hazard. In addition, the queue management logic records a reservation for the load-reserve instruction by setting the reservation valid field of an entry in the load queue associated with the load-reserve instruction. Thus, the load queue, which is utilized to detect and correct data hazards resulting from out-of-order execution of load instructions, is also advantageously utilized to manage reservations.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
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Bracewell & Patterson L.L.P.
Chan Eddie
Emile Volel
Huisman David J.
International Business Machines - Corporation
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