Patent
1997-06-11
1999-08-17
Lim, Krisna
395391, G06F 938
Patent
active
059406020
ABSTRACT:
A superscalar microprocessor is provided that includes a predecode unit configured to predecode variable byte-length instructions prior to their storage within an instruction cache. The predecode unit is configured to generate a plurality of predecode bits for each instruction byte. The plurality of predecode bits associated with each instruction byte include an end bit and an ROP bit that indicates a number of microinstructions required to implement the instruction. The plurality of predecode bits are collectively referred to as a predecode tag. An instruction alignment unit then uses the predecode tags to identify microinstructions. The instruction alignment unit dispatches the microinstructions simultaneously to a plurality of decode units which form fixed issue positions within the superscalar microprocessor. Because the instruction alignment unit identifies microinstructions, the multiplexing of instructions from the instruction alignment unit to the decoders is simplified. Accordingly, relatively fast multiplexing may be attained, and high performance may be accommodated.
REFERENCES:
patent: 4044338 (1977-08-01), Wolf
patent: 4453212 (1984-06-01), Gaither et al.
patent: 4807115 (1989-02-01), Torng
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 4928223 (1990-05-01), Dao et al.
patent: 5053631 (1991-10-01), Perlman et al.
patent: 5058048 (1991-10-01), Gupta et al.
patent: 5101341 (1992-03-01), Circello et al.
patent: 5129067 (1992-07-01), Johnson
patent: 5136697 (1992-08-01), Johnson
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5226130 (1993-07-01), Favor et al.
patent: 5233696 (1993-08-01), Suzuki
patent: 5337415 (1994-08-01), DeLano et al.
patent: 5438668 (1995-08-01), Coon et al.
patent: 5459844 (1995-10-01), Eickemeyer et al.
patent: 5499204 (1996-03-01), Barrera et al.
patent: 5513330 (1996-04-01), Stiles
patent: 5537629 (1996-07-01), Brown et al.
patent: 5560028 (1996-09-01), Sachs et al.
patent: 5566298 (1996-10-01), Boggs et al.
patent: 5586276 (1996-12-01), Grochowski et al.
patent: 5586277 (1996-12-01), Brown et al.
patent: 5598544 (1997-01-01), Ohshima
patent: 5600806 (1997-02-01), Brown et al.
patent: 5630082 (1997-05-01), Yao et al.
patent: 5644744 (1997-07-01), Mahin et al.
patent: 5651125 (1997-07-01), Witt et al.
patent: 5689672 (1997-11-01), Witt et al.
patent: 5758114 (1998-05-01), Johnson et al.
patent: 5758116 (1998-05-01), Lee et al.
patent: 5819059 (1998-10-01), Tran
patent: 5822558 (1998-10-01), Tran
Intel 1994 Pentium Processor Family User's Manual, vol. 1: Pentium Processor Family Data Book, pp. 2-1 through 2-4.
Michael Slater, "AMD's K5 Designed to Outrun Pentium," Microprocessor Report, vol. 8, No. 14, Oct. 24, 1994, 7 pages.
Sebastian Rupley and John Clyman, "P6: The Next Step?," PC Magazine, Sep. 12, 1995, 16 pages.
Tom R. Halfhill, "AMD K6 Takes On Intel P6," BYTE, Jan. 1996, 4 pages.
Minigawa, et al., "Pre-Decoding Mechanism For Superscalar Architecture," Proceedings IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, May 9-10, 1991, pp. 21-24.
Tomasulo, "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," IBM Journal, Jan. 1967, pp. 25-33.
U.S. Patent Application No. 08/873,344, filed Jun. 11, 1997.
Narayan Rammohan
Tran Thang M.
Advanced Micro Devices , Inc.
Kivlin B. Noel
Lim Krisna
Merkel Lawrence J.
Vu Viet
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