Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2001-05-25
2004-05-04
Nhu, David (Department: 2818)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S099000, C438S795000
Reexamination Certificate
active
06730522
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method of forming a solid of a ferroelectric or a high dielectric material represented by a ferroelectric thin film employed in a semiconductor device, such as a ferroelectric memory. The present invention also relates to a method of manufacturing a semiconductor device, such as a ferroelectric memory.
BACKGROUND ART
A ferroelectric memory is a non-volatile storage device employing a ferroelectric film as a charge holding capacitor, and excels in high speed, low power consumption, high integration and rewriting resistance characteristics. A polarization induced by applying an electric field to the ferroelectric film remains after the electric field is lost. This makes it possible to achieve a non-volatile storage function.
FIG. 16
is a cross section showing a cell structure of the ferroelectric memory. A semiconductor substrate
1
is provided with an element forming region on its principal surface, which is isolated by a field oxide film
2
, and impurity diffusion layers
3
and
4
spaced apart from each other are formed therein while a gate electrode
6
is formed on the principal surface of the semiconductor substrate
1
in the spacing between the impurity diffusion layers
3
and
4
by interposing a gate insulation film
5
. In this manner, a transistor TR is formed.
The gate electrode
6
is coated by a first interlayer insulation film
7
, over which a capacitor structure C such that sandwiches a ferroelectric film
10
between a lower electrode
11
and an upper electrode
12
is provided.
The upper electrode
12
is coated by a second interlayer insulation film
8
. A first aluminum wire
9
formed on the second interlayer insulation film
8
is brought into contact with the upper electrode
12
and impurity diffusion layer
4
through contact holes
14
and
15
, respectively, thereby electrically connecting the upper electrode
12
and impurity diffusion layer
4
.
In the ferroelectric memory of this cell structure, the impurity diffusion layer
3
forms a bit line, and the gate electrode
6
and lower electrode
11
form a word line and a plate line, respectively. Hence, by applying an adequate writing voltage across the bit line (impurity diffusion layer
3
) and plate line (lower electrode
11
) while applying a selective voltage to the word line (gate electrode
6
) so as to allow conduction in the transistor TR, an electric field can be applied to the ferroelectric film
10
. Consequently, a polarization can be induced in the ferroelectric film
10
in an amount corresponding to the direction and intensity of the applied electric field.
At the time of reading, an adequate selective voltage is applied to the word line (gate electrode
6
) so as to allow conduction in the transistor TR, while applying an adequate reading voltage to the plate line (lower electrode
11
). A potential appearing in the bit line (impurity diffusion layer
3
) at this point takes either one of two different potentials depending on the direction of the polarization in the ferroelectric film
10
. Based on the foregoing, it is possible to check whether the cell is in the “1” state or “0” state.
In case that a multi-layer wiring is necessary as is shown in
FIG. 16
, the first aluminum wire
9
is further coated by a third interlayer insulation film
16
. Then, a second aluminum wire
17
is additionally formed on the third interlayer insulation film
16
, and connected to the first aluminum wire
9
through a contact hole
18
. Further, the second aluminum wire
17
is coated by a protection film
19
.
Generally, complex oxide ferroelectrics represented by those based on PZT (Pb(Zr,Ti)O
3
) and those based on SBT (SrBi
2
Ta
2
O
9
) are generally used as the materials of the ferroelectric film. Thin films of these ferroelectrics are formed by, for example, the sol-gel method. The sol-gel method is defined as a method of obtaining a necessary film by coating a liquid (sol) of a raw material over a substrate followed by calcining by means of annealing. In the sol-gel method of PZT, for example, a solution of organic compounds containing metal elements, that is, Pb(CH
3
COO)
2
.3H
2
O, Zr(n—OC
4
H
9
)
4
, and Ti(i—OC
3
H
7
)
4
, in a solvent of 2-methoxy ethanol is used as a starting material. The organic compound solution is spin-coated over the substrate and dried at 150° C. to 180° C., after which precalcining is carried out for 30 minutes at 400° C. in a drying air atmosphere. This process is repeated until a predetermined film thickness is achieved, and finally, annealing at 600° C. to 700° C. is carried out to crystallize the film entirely.
However, crystallization at such high temperatures deteriorates element characteristics of the transistor TR formed beforehand, besides, mutual-diffusion of film materials at the interfaces between the ferroelectric film
10
and the upper and lower electrodes
11
and
12
causes characteristics deterioration of the ferroelectric film
10
itself. For this reason, a ferroelectric memory with satisfactory characteristics is not necessarily achieved.
The reason why the crystallization at such high temperatures is necessary is because the pre-crystallized film includes residual organic substances. Although the precalcining at a temperature of approximately 400° C. can remove the organic substances to some extent, annealing at a temperature exceeding 700° C. is necessary in order to remove the organic substances from the film in a satisfactory manner. Such a high temperature, however, causes crystallization of the film materials, thereby causing not only a loss of the purpose of the precalcining, but also more serious damages to the transistor TR formed on the semiconductor substrate
1
.
Therefore, there is no conventional method of forming a ferroelectric film that has been crystallized satisfactorily by annealing at low temperatures, which makes it impossible to provide a ferroelectric memory with satisfactory characteristics.
On the other hand, because the complex oxide ferroelectrics represented by those based on PZT (Pb(Zr,Ti)O
3
) and those based on SBT (SrBi
2
Ta
2
O
9
) are oxides, they are vulnerable to a reduction atmosphere. Hence, if they undergo an interlayer insulation film forming process that uses SiH
4
, a H
2
sintering process aiming at stabilizing the P—N junction or improving ohmic characteristics at a contact, etc., the capacitor characteristics may deteriorate.
To be more specific, in case of forming the cell structure shown in
FIG. 16
, because the second and third interlayer insulation films
8
and
16
and the protection film
19
are formed after the ferroelectric film
10
is formed, it is unavoidable for the ferroelectric film
10
to be exposed in a reduction atmosphere.
In addition, because the ferroelectrics also have the piezoelectric characteristics, they are quite sensitive to stress applied from the interlayer insulation film or protection film, thereby possibly causing biased characteristics.
Hence, the ferroelectric film
10
is under the stress applied from the upper electrode
12
, second and third interlayer insulation films a and
16
, first and second aluminum wires
9
and
17
, and protection layer
19
, all of which being formed in the steps carried out after the ferroelectric film
10
is formed, and for this reason, capacitor characteristics as designed may not be necessarily achieved.
Further, in the steps carried out after the ferroelectric film
10
is formed, etching is indispensable to pattern the upper electrode
12
, first and second aluminum wires
9
and
17
, etc. However, this etching causes damages to the ferroelectric film
10
, which is one of the factors that deteriorate the capacitor characteristics of the ferroelectric film
10
.
It has been known that the characteristics deterioration of the ferroelectric film
10
as discussed above is restorable by annealing at 550° C. to 600° C. in an oxygen atmosphere. However, annealing at such high temperatures not only causes characteristics deterioration of the transistor TR, but also mel
Fujimori Yoshikazu
Nakamura Takashi
Nhu David
Rabin & Berdo P.C.
Rohm & Co., Ltd.
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