Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device
Reexamination Certificate
2002-07-12
2004-07-06
Ho, Hoai (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
Having specific type of active device
C257S203000, C257S204000, C257S207000, C257S378000, C326S101000
Reexamination Certificate
active
06759698
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and particularly to improvement in a cell structure primarily used in the automatic placement and routing in the layout design of a semiconductor integrated circuit.
2. Description of Related Art
FIG. 8
is a plan view showing a cell structure used for designing a conventional semiconductor integrated circuit. In
FIG. 8
, the reference numeral
100
designates a cell, which is an inverter in this case. The reference numeral
101
designates a power supply trunk placed in the cell
100
, and
102
designates a ground trunk placed in the cell
100
. The reference numeral
103
designates a metal line of the source electrode of a PMOSFET placed at a power supply side; and
104
designates a contact connecting the metal line
103
to the active region
105
of the PMOSFET. The metal line
103
is also connected to the power supply trunk
101
. The reference numeral
106
designates the active region of an NMOSFET; and
107
designates a metal line of the source electrode of the NMOSFET placed on the ground side. The metal line
107
is connected to the active region
106
via the contacts
104
. The reference numeral
108
designates a gate electrode of the PMOSFET;
109
designates a gate electrode of the NMOSFET; and
110
designates a metal line for interconnecting the gate electrodes
108
and
109
. The metal line
110
functions as an input pin of the inverter. The reference numeral
111
designates a metal line at the output side; and
112
designates a contact for connecting the metal line
111
to the active regions
105
and
106
.
Next, the outline of the conventional cell will be described.
As shown in
FIG. 8
, the cell used for the conventional automatic placement and routing is configured such that the power supply trunk
101
is connected to the metal line
103
of the source electrode on the power supply side in advance, and the ground trunk
102
is connected to the metal line
107
of the source electrode on the ground side in advance. Thus, the cell
100
constituting the inverter operates at the power supply potential fed via the power supply trunk
101
.
When a plurality of cells
100
are automatically placed adjacently, the cells
100
are connected to the power supply trunk
101
and ground trunk
102
that supply the common potential because of the routing structure described above. Accordingly, two adjacent cells
100
are connected in common to the power supply and ground with the same potentials without exception.
With the configuration as described above, the conventional semiconductor integrated circuit has the following problem. Because the power supply trunk
101
is connected to the metal line
103
of the source electrode on the power supply side, and the ground trunk
102
is connected to the metal line
107
of the source electrode on the ground side within the cell
100
in advance, and hence the power supply trunk and ground trunk are used in common, it is unavoidable that the adjacent cells
100
have the same potential. Accordingly, it is impossible to connect the power supplies with different potentials to the adjacent cells
100
. As a result, to control the power supply voltage individually for each cell
100
, the cells
100
that are connected to power supplies with different potentials must be separated, thereby complicating the layout.
SUMMARY OF THE INVENTION
The present invention is implemented to solve the foregoing problem. It is therefore an object of the present invention to provide a semiconductor integrated circuit capable of connecting the adjacent cells to a plurality of power supplies with different potentials.
According to one aspect of the present invention, there is provided a semiconductor integrated circuit including cells and potential feeders. Each cell includes a partial trunk which is used to constitute a power supply trunk and/or ground trunk, and is electrically isolated from remaining components within the cell. The potential feeders are selectively connected to the power supply trunk and/or ground trunk of any one of cell rows, and supply the components within the cells with a potential fed via the power supply trunk and/or ground trunk. Thus, the semiconductor integrated circuit can supply the adjacent cells with different potentials, thereby offering an advantage of being able to control the potentials to be supplied to the cells on a cell by cell basis with ease.
REFERENCES:
patent: 4766476 (1988-08-01), Schallenberger et al.
patent: 5514895 (1996-05-01), Kikushima et al.
patent: 5581202 (1996-12-01), Yano et al.
patent: 5698873 (1997-12-01), Colwell et al.
patent: 2003/0023936 (2003-01-01), McManus et al.
patent: 10-150175 (1998-06-01), None
patent: 10-189749 (1998-07-01), None
patent: 11-031803 (1999-02-01), None
patent: 11-224901 (1999-08-01), None
Burns Doane , Swecker, Mathis LLP
Ho Hoai
Nguyen Dao H.
Renesas Technology Corp.
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