Crosspoint switch with reduced power consumption

Communications: electrical – Selective – Decoder matrix

Reexamination Certificate

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Details

C340S002280

Reexamination Certificate

active

06737958

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to a crosspoint switch, and, more particularly, to a crosspoint switch having a power-saving bias control circuit for controlling the bias current of each switch core as a function of switch state to minimize the power consumption of the crosspoint switch, and optionally having two memory cells associated with each switch core for reducing the reconfiguration time of the crosspoint switch.
BACKGROUND OF THE INVENTION
Recent trends in data communications have necessitated the development of high-speed, reconfigurable data switches capable of routing signals to any of plural locations. Also, a known method for enhancing the processing power of a given technology is through the use of multiple processors sharing memory and input/output devices that are coupled together in a wideband communication network having a bandwidth in the range of multiple gigabits per second. In such applications, where the throughput rate of exchanging and sharing data needs to be maximized, it is desirable to have a non-blocking circuit switch that allows simultaneous data traffic at the network bandwidth. The key data routing function in such data networks is frequently performed by crosspoint switches, which allow incoming data streams to be routed to specified output channels.
Generally, a crosspoint switch for N-ports with N input and N output links consists of N×N switch elements and corresponding latches that store switch setup or connection information provided by a switch controller. Crosspoint switches are used in many applications requiring reconfigurable high-speed switch networks. A crosspoint switch is an electronic circuit that is designed to receive one or more input signals at one or more input terminals and route the signals to one or more output terminals. A controller external to the switch network is generally used to reconfigure the crosspoint switch to change the routing of the input signals to different output terminals. The function of a crosspoint switch is shown schematically in
FIG. 1
, which is a simplified block diagram illustrating the matrix fabric of a 4×4 array type crosspoint switch. Data inputs IN
1
-IN
4
enter from the left-hand side through input buffers
10
, and data outputs OUT
1
-OUT
4
exit from the bottom through output buffers
12
. Switch elements
14
, which are typically pass-gate type elements such as FETs, provide reconfigurable, non-blocking paths from the inputs to the outputs.
The crosspoint switch is an important building block for digital communications systems that are required to share expensive resources. Such switches have been used in a wide range of systems, from workstations to computer networks, packet data networks and voice (circuit and packet) switching networks. Most recently, the shift towards graphical and video information display coupled with the widespread popularity of the Internet have significantly increased the demand for bandwidth and connectivity. Although this demand can be met by increasing the number of parallel connections in a given communication system, economic factors have favored increasing the bandwidth in each connection. This is especially true with respect to fiber optic lines, which provide a particularly high-speed data communications pathway with a wide bandwidth. As a result, there is significant demand in current network applications for crosspoint switches capable of delivering multi-gigabit per second performance for each channel.
While the telephone network was originally designed for voice communications, it has been evolving into a digital network for the transmission of audio, internet data and video data. During the 1980's, new international broadband data communications standards for voice and data were formed. The resulting Synchronous Optical Network (SONET/North America), and Synchronous Digital Hierarchy (SDH/Europe and Asia) standards were defined to accommodate increasing bit rates. The baseline rate for SONET (OC-1) is 51.84 Mbps and the baseline rate for SDH (STM-
1
) is three times OC-1 or 155.52 Mbps. Currently, telcom networks operating up to OC-12 (OC-1×12) and OC-48 (2.5 Gbps) are in widespread deployment. Crosspoint switches are an integral part of such networks. Crosspoint switches for OC-12 and lower bit rates can be readily realized with silicon-based BJT or CMOS VLSI technology. One such crosspoint switch which is commercially available is model TQ8025, available from Triquint, the datasheet of which is incorporated herein by reference. At bit rates in the multi-gigabit per second range, various approaches have been used to combat effects associated with high-frequency communications, such as excessive power dissipation, jitter and crosstalk.
The explosive demand for broadband Internet access has fueled the need to increase the bandwidth of telcom networks. At present, GaAs laser drivers, preamplifiers and the like are capable of addressing bit rates of over OC-48 (2.488 Gbs) and OC-192 (9.953 Gbs), and advanced III-IV technologies are addressing OC-768 (39.13 Gbs) and higher. Crosspoint switches capable of accommodating these bit rates are needed to transform a link into a network in order to meet the connectivity requirement.
FIG. 1
illustrates the most natural realization of a crosspoint switch, which is the so-called matrix or array architecture. In the matrix architecture, a matrix of n inputs by m outputs is interconnected with switch elements
14
at each intersection.
FIG. 2
is a simplified block diagram illustrating a typical crosspoint switch
200
having a matrix architecture. The crosspoint switch
200
includes input terminals IN
1
-IN
N
coupled to receive corresponding input signals. The crosspoint switch
200
also includes output terminals OUT
1
-OUT
N
, to provide corresponding output signals. The crosspoint switch circuit
200
is used to selectively route one or more of the input signals received at the input terminals IN
1
-IN
N
to one or more output terminals OUT
1
-OUT
N
. An input buffer
202
is connected to each input terminal IN
1
-IN
N
, the output of which is connected to an input lead of each of a row of substantially identical switch cores
204
. Thus, each input terminal is connected to all of the switch cores
204
in a given row. Similarly, each output terminal OUT
1
-OUT
N
is connected to all of the switch cores
204
in a corresponding column of switch cores
204
through an output buffer
206
. A switch configuration control circuit
208
has an input port
210
coupled to receive configuration control signals CONFIG from an external controller (not shown), through which the external controller configures each crosspoint switch core
204
. The configuration control signals CONFIG are typically serial multi-bit signals that include the configuration information on an input-to-output basis (i.e., for each input signal, the configuration control signals CONFIG control which output terminal or terminals the input signal is to be routed to). Of course, the control signals can be multi-bit parallel signals. In response to the configuration control signals, control logic in the switch configuration control circuit
208
configures each switch core
204
to select one of the input signals and provide an output signal dependent on the selected input signal to output terminals OUT
1
-OUT
N
, respectively. In some applications of the crosspoint switch
200
, one or more of input terminals IN
1
-IN
N
and one or more of output terminals OUT
1
-OUT
N
are not used.
As a general rule, no two inputs of the crosspoint switch can be routed to the same output at the same time. This would constitute a contention. However, one input can be connected to several outputs. This is referred to as the broadcast mode. In either case, the total number of switches that are actually routing data for a 16×16 switch is no more than 16. In any given configuration, no more than 16 switches are always on.
To configure each switch core
204
, switch configuration control circuit
208

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