Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1999-05-20
2004-04-27
Kizou, Hassan (Department: 2662)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S395310, C370S413000
Reexamination Certificate
active
06728251
ABSTRACT:
CROSS-REFERENCE TO RELATED PATENT APPLICATION
The following European Patent application numbers are cross-referenced:
European patent application no. 97480057.5 assigned to the Assignee of the present application describes with many details the general principle of SCAL elements in switching architectures.
European patent application no. 97480098.9 permits substantially enhancing the multicasting possibilities of the switching architecture.
TECHNICAL FIELD OF THE INVENTION
The invention relates to switching systems and, more particularly, to a switching apparatus comprising a centralized Switch Core and at least one Switch Core Access Layer (SCAL) element(s) for the attachment of various Protocol Adapters.
BACKGROUND ART
Shared buffer switches have shown to be of great interest for switching small packets of data and are well adapted to the switching of Asynchronous Transfer Mode (ATM) cells although they are not limited to the ATM technology. Basically, a shared buffer switch comprises a cell storage which is used for storing the cells presented on one input port of the Switch. An appropriate mechanism is used for extracting the cell from the shared buffer and for directing the latter to one or more output ports of the switch. By using different output queues, each one dedicated to one output port of the switch, it is made possible to achieve a very simple multicasting effect in the switching process.
An important aspect of modern switches resides in their capability to permit attachment of a great number of Protocol Adapters which are located at different areas, generally remote, with respect to the Switch Core. A technique used for achieving this goal is based on the provision of Switch Core Access Layers (SCAL) elements which are distributed at different areas and to which are connected the Protocol Adapters.
In order to enhance multicasting capability, SCAL elements were given an additional important function. They introduce a specific processing in the cell for preparing the latter to the switching process within the centralized Switch Core. This is based on the introduction within the cell of a specific field, a so called bitmap which is reserved for receiving at appropriate time a particular value for controlling the routing process. More particularly, the bitmap field is assigned its first actual value when the cell enters the switch core, and also at the output of the latter, before the cell is transmitted again to the SCAL element (i.e., the transmit part of the SCAL).
Another aspect of modern switches resides in their capacity to allow attachments of a great variety of Protocol Adapters, operating at different speeds or different formats of cells (particularly the size of the cell may differ). This is more particularly true as the switching rate will continuously increase, resulting in the coexistence of modern adapters and more classical ones.
At last, the SCAL elements must be adapted to the structure of high-speed modern Switch cores, and particularly those operating in speed expansion. The speed expansion is a technique that was designed in switching systems for going over the possibilities and physical limitations of a given technology. Speed expansion permits switching rates of more than 1 Giga bps. This is achieved by an effective combination of several distinctive individual switching modules together (e.g., four modules) in order to form an aggregate high-rate Switching structure or Switch Core. For that purpose, the cell is divided in Logical Units (LU) which are separately transported to the centralized Switch Core, and each Logical Unit is directed to one dedicated switching module. By means of an appropriate mechanism, the four modules can be coupled and synchronized under the control of a master module which permits simultaneously routing the four LUs towards a same destination port, thus allowing the routing of the whole cell. This obviously permits an increase of the overall switching speed, although the semiconductor technology remains unchanged. A detailed description of this architecture can be found in European application no. 97480057.5 and no. 97480056.7, which contents are herein incorporated by simple reference.
It results from the observations above that the SCAL elements are essential features of modern switching architectures. They play key functions and, therefore, most aspects of the switching systems depend on the efficiency of the SCAL elements. There is a strong desire for a SCAL element that allows attachment of a wide number of different Protocol Adapters, having different format and speed characteristics, and supporting the increasing speed of the speed expansion technique. The SCAL should additionally permit an easy introduction of the bitmap field which is now an essential requirement in modern switches.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a Switch Core Access Layer (SCAL) element that is versatile enough to permit attachment of a great number of different Protocol Adapters having characteristics of different speeds and formats.
It is another object of the invention to provide a programmable remote SCAL element for interfacing a Switch Core and allowing high speed transmissions.
It is still another object of the invention to provide a SCAL element permitting attachment to one or more Protocol Adapters at the same time, and providing the introduction of a bitmap field without jeopardizing the speed rate.
These and other objects of the invention are achieved by the switching apparatus comprising a centralized Switch Core and at least one SCAL element for the attachment of various Protocol Adapters in accordance with the present invention. Basically, the Switch Core and the SCAL communicate with each other via n parallel serial links with each one transmitting a Logical Unit. Each SCAL comprises in both the receive and the transmit part at least one input for receiving cells from said Protocol Adapter; a set of n FIFO queues for storing the cells into n parallel busses; and a set of n RAM storages, with each RAM being associated with one Logical Unit.
First multiplexing means receives the contents of the parallel busses for performing simultaneously n WRITE operations into the n RAM storages under control of a first set of n tables. There is provided second multiplexing means for making READ operations from said n RAM storages under control of a second set of n tables. By appropriate arrangement of the two sets of tables, which are chosen complementary, the cells which are conveyed through the first multiplexing means, the RAMs and the second multiplexing means are subject to a cell rearrangement that includes a bitmap field introduction and that produces the n Logical Units.
When two bytes which are processed in parallel have to be loaded at the same time in the same RAM storage because they are intended to be transported into a same associated Logical Unit, one particular byte is accidentally stored into one RAM available for a Write operation by means of said first set of tables. This causes an alteration to the normal association between the n RAMs and the n Logical Units, which alteration is re-established by means of the second set of tables.
Preferably, the number of Logical Units is fixed to four, which is also the number of the RAMs. In a preferred embodiment, the first multiplexing means is controlled by means of a set of four control Registers, with each register comprising a first field (MUXc) defining in which RAM the associated input byte will be written, a second field (OFFSET) defining the particular location to store said byte, and a third field for storing an incrementing value (WAR) characterizing the cell buffer. For each cycle, the first and second field of said control registers are provided by said first set of tables.
This has the strong advantage of allowing the use of every clock cycle since four parallel write operations and four parallel read operations can always be executed.
REFERENCES:
patent: 5287358 (1994-02-01), Nakayama
patent: 5321691 (1994-06-01), Pash
Blanc Alain
Orengo Gerard
Poret Michel
International Business Machines - Corporation
Kizou Hassan
Munoz-Bustamante Carlos
Odland David
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