Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2002-09-20
2004-09-14
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S511000, C257S556000, C257S559000, C438S335000, C438S421000, C438S422000
Reexamination Certificate
active
06791155
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor manufacturing and, more particularly, to a stress-relieved shallow trench isolation (STI) structure and a method for fabricating the same.
2. Description of the Related Art
The fabrication of integrated circuits typically involves placing numerous devices on a single semiconductor substrate such as a silicon substrate. Isolation structures are used to electrically isolate one device from another. Individual devices are then interconnected by forming conducting lines over the isolation structures.
Among these isolation structures, a Shallow Trench Isolation (STI) structure has become popular because the device isolation area is small, and hence the resulting trench can be well adapted for device miniaturization. Typically, STI is formed by etching a shallow trench in a silicon substrate between areas where active devices are to be formed, and thereafter typically filling the trenches with a dielectric material.
However, conventional STI processes still have drawbacks. For example, defects can be formed in the silicon substrate due to the thermo-mechanical stress placed on the silicon substrate and the dielectric material during the STI process. The defects can be formed especially during the subsequent processes involving thermal cycles, such as various thermal oxidation, and source/drain implantation activation anneal processes.
The causes of the thermo-mechanical stress can be explained by several theories. One such theory is that the uneven volumetric expansion and contraction of the trench volume and filled dielectric volume, due to the differences between the coefficients of the thermal expansion of Si-substrate and the trench dielectric, induces large stress pinching at the interface of the Si-substrate and the trench dielectric. Furthermore, additional stress can be applied to the sidewalls of the trench during subsequent thermal processes. That is, the trench sidewalls can be subjected to oxidation, increasing the trench dielectric volume, which in turn, builds up the stress.
The stress becomes even more severe when a high-density plasma (HDP) oxide layer, which is now gaining popularity as a gap-fill material, is employed to fill the trench. The HDP oxide layer is very dense and is very susceptible to any thermal cycles applied on the STI structure. The high-density characteristic is the direct result of employed ions striking during the deposition of an HDP-film, so the HDP film filled in the STI structure can be considered as “Full”-fill, and any extra volumetric expansion will induce “Over”-fill. As described by Stiffler et al., “Oxidation-Induced Defect Generation in Advanced DRAM structures,” IEEE Trans. On Electron Devices, vol. 37, 1990, pp. 1253-1257, the trench sidewall oxidation after trench dielectric fill can be viewed as driving a wedge between the Si-substrate and the trench dielectric, which severely stresses the Si-substrate.
Such stress is detrimental to the integrity of the active Si, especially on the sidewalls and bottom of STI, causing micro defects, i.e., dislocation due to damage of the silicon lattice, or shallow pits on the bottom and sidewalls of the trench, and on the active region of the semiconductor substrate. Thus, STI integrated devices present large leakage current problems, especially affecting the fabrication of high-density semiconductor devices. Such an increase in leakage current adversely impacts the performance and operability of the semiconductor devices. This problem is discussed in a paper entitled “Modeling of Cumulative Thermo-Mechanical Stress (CTMS) Produced by the Shallow Trench Isolation Process for 1 Gb DRAM and beyond,” by Tai-Kyung Kim et al., IEDM Tech. Dig., 1998, pp. 145-148, 1998. Saino et al. shows the severely decreased data retention time with increasing temperature, which is correlated with the overly stressed Si-substrate, as well as high density of stress-induced dislocations, even with simple N
2
densification (See IEDM Tech. Dig., 1998, pp. 149-152). So, the STI is a very delicate and sensitive structure, and worse yet, it is also formed during the early stage of the whole process flow for IC fabrication.
Much effort has been devoted to overcome such stress/dislocation issues associated with STI. For example, there have been various attempts to optimize process flows, device tuning to work around this sensitive STI structure to overcome, for example, the stress-induced leakage current problem. For instance, as described in U.S. Pat. No. 6,281,081, Chien et al. teaches a low energy phosphorus implant for source/drain formation. However, these attempts severely limit device engineering freedom for performance optimization.
Accordingly, it would be desirable to provide a method of minimizing or reducing mechanical stress in current standard STI processes, from the early stage of the STI formation.
SUMMARY OF THE INVENTION
A shallow trench isolation (STI) structure in a semiconductor substrate and a method for forming the same are provided. A trench is formed in a semiconductor substrate. A first dielectric layer is formed on sidewalls of the trench. The first dielectric layer is formed thicker at a top portion of the sidewalls than a bottom portion of the sidewalls, leaving an entrance of the trench open to expose the trench. A second dielectric layer is conformally formed on the first dielectric layer to close the entrance, thus forming a void buried within the trench.
With the present invention, the stress between the trench dielectric layer and the surrounding semiconductor substrate during thermal cycling can be substantially reduced by allowing the trench dielectric layer to be expanded or shrunk with the surrounding substrate without generating stress. This is believed to be possible because the buried void acts as a buffer structure during thermal cycling.
The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention that proceeds with reference to the accompanying drawings.
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T. Kuroi, T. Uchida, K. Horita, M. Sakai, Y. Itoh, Y. Inoue and T. Nishimura “Stress Analysis of Shallow Trench Isolation for 256MDRAM and beyond,” IEDM Tech. Dig. 1998, pp. 141-144.
Tai-Kyung Kim, Do-Hyung Kim, Jae-Kwan Park, Tai Su Park, Young-Kwan Park, Hoong-Joo Lee, Kang-Yoon Lee, Jeong-Taek Kong, and Jong-Woo Park “Modeling of Cumulative Thermo-Mechanical Stress (CTMS) Produced by the Shallow Trench Isolation Process for 1Gb DRAM and beyond,” IEDM Tech. Dig. 1998, pp. 145-149.
K. Siano, K. Okonogi, S. Horiba, M. Sakao, M. Komuro, Y. Takaishi, T. Sakoh, K. Yoshida and K. Koyama “Control of Trench Sidewall Stress in Bias ECR-CVD Oxide-Filled STI for Enhanced DRAM Data Retention Time,” IEDM Tech. Dig. 1998, pp. 149-152.
Foley Gary
Lee Shih-Ked
Lo Guo-Qiang (Patrick)
Schorr Brian
Integrated Device Technology Inc.
Marger & Johnson & McCollom, P.C.
Nelms David
Nguyen Dao H.
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