Metal working – Method of mechanical manufacture – Electrical device making
Reexamination Certificate
2002-01-04
2004-05-11
Vo, Peter (Department: 3729)
Metal working
Method of mechanical manufacture
Electrical device making
C029S613000, C029S619000, C338S309000, C438S330000
Reexamination Certificate
active
06732422
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to a layout and method to improve linearity and reduce voltage coefficient of resistance for resistors used in mixed-mode analog/digital applications.
(2) Description of Related Art
U.S. Pat. No. 6,103,622 to Huang describes a silicide process for mixed-mode analog digital/devices.
U.S. Pat. No. 5,924,011 to Huang describes a method for fabricating mixed analog/digital devices using a silicide process.
U.S. Pat. No. 6,054,359 to Tsui et al. describes a method for fabricating high sheet resistance polysilicon resistors.
U.S. Pat. No. 5,885,862 to Jao et al. describes a poly-load resistor for a static random access memory, SRAM, cell.
A paper entitled” Characterization of Polysilicon Resistors in Sub-0.25 &mgr;m CMOS USLI Applications” by Wen-Chau Liu, Member IEEE, Kong-Beng Thei, Hung-Ming Chuang, Kun-Wei Lin, Chin-Chuan Cheng, Yen-Shih Ho, Chi-Wen Su, Shyh-Chyi Wong, Chih-Hsien Lin, and Carlos H. Diaz, IEEE Electron Device Letters, Vol. 22, No. 7, pages 318-320, July 2001 describes characterization of polysilicon resistors.
SUMMARY OF THE INVENTION
High performance resistors are important devices in the design of mixed-mode analog/digital circuits. A number of parameters are of key importance for these resistors such as resistor linearity, insensitivity of resistance to thermal processing steps, and voltage coefficient of resistance (VCR).
It is a principal objective of at least one embodiment of this invention to provide a method of forming a resistor having good linearity, thermal process stability, and low voltage coefficient of resistance (VCR).
It is another principal objective of at least one embodiment of this invention to provide a resistor layout for a resistor having good linearity, thermal process stability, and low voltage coefficient of resistance (VCR).
These objectives are achieved by first forming a resistor from a first conducting material such as doped polysilicon. The resistor has a rectangular first resistor element having a width, a length, a first end, and a second end; a second resistor element having a first edge and a second edge wherein the first edge of the second resistor element contacts the entire width of the first end of the first resistor element; a third resistor element having a first edge and a second edge wherein the first edge of the third resistor element contacts the entire width of the second end of the first resistor element; a fourth resistor element having a contact edge wherein the contact edge of the fourth resistor element contacts the entire the second edge of the second resistor element; and a fifth resistor element having a contact edge wherein the contact edge of the fifth resistor element contacts the entire the second edge of the third resistor element. A layer of protective dielectric is then formed over the first, second, and third resistor elements leaving the fourth and fifth resistor elements exposed.
The first conducting material in the exposed fourth and fifth resistor elements is then changed to a second conducting material, which is a silicide, using a silicidation process. The second conducting material is a silicide such as titanium silicide. The second conducting material has a higher conductivity than the first conducting material. The higher conductivity second conducting material forms low resistance contacts between the second and fourth resistor elements and between the third and fifth resistor elements. The second and third resistor elements are wider than the first resistor element and provide a low resistance contacts to the first resistor element, which is the main resistor element. This provides low voltage coefficient of resistance and good resistor linearity.
The protective dielectric over the first, second, and third resistor elements prevents the resistor from silicidation during subsequent process steps.
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patent: 6054359 (2000-04-01), Tsui et al.
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Wen-Chau Liu et al., “Characterization of Polysilicon Resistors in Sub-0.25 &mgr;m CMOS ULSI Applications”, Member IEEE, IEEE Electron Device Letters, vol. 22, No. 7, pp. 318-320, Jul. 2001.
Lin Chih-Hsien
Thei Kong-Beng
Wong Shyh-Chyi
Ackeraman Stephen B.
Nguyen Donghai D.
Prescott Larry J.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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