Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2002-09-25
2004-05-25
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189050, C365S239000
Reexamination Certificate
active
06741521
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and, particularly, to a semiconductor memory device capable of operating synchronously with the rising and falling edges of an external clock and reading data at high speed.
2. Description of the Background Art
Among synchronous dynamic random access memories (SDRAMs) operating synchronously with a clock signal supplied from the outside, one which inputs/outputs data synchronously with the rising and falling edges of an external clock signal is called a double data rate synchronous dynamic random access memory (DDR SDRAM). The DDR SDRAM has already been standardized. The DDR SDRAM of the first generation among the standardized DDR SDRAMs is called a DDR-I.
FIG. 36
is an operation waveform chart showing data output timings in the case of reading data from a DDR SDRAM called DDR-I.
The operation waveform chart of
FIG. 36
shows a case where CAS latency CL is 2.5 and a burst length BL is 4. The CAS latency denotes the number of cycles (each cycle starts at the rising edge of an external clock signal EXTCLK and ends at the next rising edge) in a period from a DDR SDRAM receives a command READ (command for reading data) from the outside at time t3 until read data is started to be output at time t8. The burst length denotes the number of bits of data successively read in the period from time t8 to t12 in response to command READ.
The DDR SDRAM outputs data DQ as read data and a data strobe signal DQS synchronously with external clock signals EXTCLK and EXTZCLK. External clock signal EXTZCLK is a clock signal complementary to external clock signal EXTCLK. Data strobe signal DQS is a signal used as a timing of latching data DQ on an external controller side for receiving data DQ.
FIG. 37
is a schematic block diagram for explaining a clock transmission path from a DLL circuit
1500
in a conventional DDR SDRAM to a data output circuit
1550
.
Referring to
FIG. 37
, DLL circuit
1500
outputs a clock signal CLK_PF at a timing earlier than the rising edge of external clock signal EXTCLK by predetermined time, and a clock signal CLK_NF at a timing earlier than the rising edge of external clock signal EXTZCLK by predetermined time. The predetermined time is expressed as a backward amount Ta in
FIGS. 40 and 42
which will be described later. A repeater
1520
amplifies the signal level of each of clock signals CLK_PF and CLK_NF and outputs clock signals CLK_P and CLK_N.
A plurality of data output circuits
1550
are provided based on a word configuration to which the DDR SDRAM is adapted.
FIG. 37
shows a case where 16 data output circuits
1550
for outputting data signals DQ0 to DQ15, respectively, are provided in a semiconductor memory device.
Each of data output circuits
1550
latches data read from a memory cell array to a data bus DB in accordance with an internal signal NZPCNT determined on the basis of the CAS latency and clock signals CLK_P and CLK_N, amplifies the data, and outputs amplified data.
As shown in
FIG. 37
, generally, a signal path from DLL circuit
1500
to data output circuit
1550
has a tree shape. The circuits and interconnections disposed so that data output timings of plural data output circuits
1550
are not largely different from each other. Generally, one repeater
1520
is disposed per eight data output circuits or four data output circuits.
FIG. 38
is a block diagram showing the configuration of data output circuit
1550
in FIG.
37
.
Referring to
FIG. 38
, data output circuit
1550
includes: an amplifying circuit
1554
for amplifying a data signal transmitted via data bus DB; a parallel/serial converting circuit
1556
for rearranging plural data supplied in a group from amplifying circuit
1554
; an output data latch
1558
for latching an output of parallel/serial converting circuit
1556
; an output driver
1530
for outputting data signal DQ to a terminal in accordance with an output of output data latch
1558
; and a clock generating circuit
1552
for supplying clocks to amplifying circuit
1554
, parallel/serial converting circuit
1556
, and output data latch
1558
.
Clock generating circuit
1552
outputs signals CLKQ, CQP, CQN, CLKO, and ZCLKO in accordance with clock signals CLK_P and CLK_N supplied from DLL circuit
1500
via repeater
1520
in FIG.
37
and internal signal NZPCNT determined on the basis of the CAS latency.
Amplifying circuit
1554
includes an amplifier RA0 for amplifying data signals transmitted via data buses DB0 and ZDB0 and outputting amplified signals to read data buses RD0 and ZRD0 and an amplifier RA1 for amplifying data signals transmitted via data buses DB1 and ZDB1 and outputting amplified signals to read data buses RD1 and ZRD1.
Data bus DB0 in
FIG. 38
is one of data buses DB0<0> to DB0<15> in
FIG. 37
, and data bus DB1 in
FIG. 38
is one of data buses DB1<0> to DB1<15> in FIG.
37
. “Z” attached to the head of a signal name or data bus name denotes a complementary or inversion signal, and data bus ZDB0 indicates a data bus complementary to data bus DB0. Similarly, data bus ZDB1 denotes a data bus complementary to data bus DB1. By using a pair of complementary data buses, data transmission can be performed by a signal of a small amplitude.
2-bits data read from the memory cell array to the pair of data buses DB0 and ZDB0 and the pair of data buses DB1 and ZDB1 is transmitted as complementary data signals of a small amplitude.
In the case of the DDR-I, data is read from the memory cell array in the external clock cycles on condition that a 2-bits prefetch operation of reading 2-bits data to each data output circuit in a single reading operation is performed. Specifically, data of two bits is read in a group from the memory cell array and output to data output circuit
1550
every cycle of the external clock. In data output circuit
1550
, the 2-bits data is ordered and output to the outside every half cycle of the external clock.
Amplifier RA0 operates in the cycles of the external clock synchronously with clock signal CLKQ supplied from clock generating circuit
1552
, amplifies the data signals read from the memory cell array to data buses DB0 and ZDB0, and outputs the resultant signals to parallel/serial converting circuit
1556
.
In a manner similar to amplifier RA0, amplifier RA1 operates in the cycles of the external clock synchronously with clock signal CLKQ. Amplifier RA1 amplifies the data signals read from the memory cell array to data buses DB1 and ZDB1 at the same timing as that of reading data signals to data buses DB0 and ZDB0, and outputs the amplified data signals to parallel/serial converting circuit
1556
.
Parallel/serial converting circuit
1556
orders data of two bits received from amplifiers RA0 and RA1 and outputs the resultant to output data latch
1558
.
Output data latch
1558
operates in half cycles of the external clock synchronously with clock signals CLKO and ZCLKO supplied from clock generating circuit
1552
, latches the data signals received via read data buses RDD and ZRDD from parallel/serial converting circuit
1556
, and outputs signals ZRDH and ZRDL.
Output driver
1530
outputs data signal DQ to drive a terminal in accordance with signals ZRDH and ZRDL which change every half cycle of the external clock.
When data is ordered by parallel/serial converting circuit
1556
, the least significant bit (LSB) CA0 of a column address supplied together with command READ to the semiconductor memory device is referred to. In
FIG. 38
, a signal EZORG obtained by properly shifting address bit CA0 in accordance with the CAS latency is used by parallel/serial converting circuit
1556
.
Since 2-bits prefetch operation is performed, one more address is generated internally from the column address supplied from the outside. In the case where address bit CA0 is 0, an “even-number” address corresponding to the column address supplied and an “odd-number” address obtained by incrementing the column address by one are generated on the inside.
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