Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-04-15
2004-09-07
Karlsen, Ernest (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
Reexamination Certificate
active
06788092
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device test board and a method for testing an integrated circuit (IC) package, and more particularly to a test board and a testing method for an integrated circuit package having solder bumps.
2. Description of the Related Art
As electronic devices have become more smaller and thinner, the velocity and the complexity of chip become more and more higher. Accordingly, a need has arisen for higher package efficiency. To meet the need, integrated circuit packages using solder bumps as external connection terminals have been developed by the semiconductor industry.
The above described integrated circuit package are subjected to various tests such as a solder joint reliability test with the solder bumps connected to a test board.
A conventional semiconductor device test board
100
, shown in
FIG. 1
, includes a plurality of contact pads
110
as denoted with A
1
to U
21
in
FIG. 1 and a
plurality of test pads
120
as denoted with
1
to
17
in FIG.
1
. The contact pads
110
and the test pads
120
are all interconnected by conductive traces
130
. The contact pads
110
are designed to be connected to the solder bumps (not shown) provided on an integrated circuit package to be tested. Accordingly, when the integrated circuit package is mounted on the test board
100
, the solder bumps provided on the integrated circuit package are connected by reflow soldering to the contact pads
110
of the test board
100
. Thereafter, the solder joint reliability test is conducted by using an ohmmeter to determine whether the electrical connections are complete in such a connected state. If the measured resistance of the major test pads S and E is larger than a predetermined value, it means that at least one solder joint fails in the test. In this situation, every pair of test pads (such as ½, ⅔ . . . illustrated in
FIG. 1
) will be probed to measure their resistance so as to find out which group of solder joints fails in the test.
Then, a failure analysis is conducted to find out which solder joint fails in the test. First, the integrated circuit package mounted on the test board is embedded in a piece of resin, and then a grinding operation is conducted to expose the cross section of the solder joints. Finally, a scanning electron microscope (SEM) is utilized to observe the cross section.
It is noted that the contact pads
110
connected between one pair of test pads
120
are randomly distributed in different rows. Since the grinding operation must be conducted from outer rows to inner rows, there is a problem that the SEM failure analysis becomes a time-consuming process when the test board
100
shown in
FIG. 1
is used.
Consequently, there is a need existed for a semiconductor device test board and a method for testing an integrated circuit package which overcomes, or at least reduces the above-mentioned problems of the prior art.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a test assembly including a package substrate and a test board for an integrated circuit package and a method of testing an integrated circuit package which can significantly reduce the time for conducting the SEM failure analysis.
To achieve the above listed and other objects, the package substrate of the present invention is provided with a plurality of first contact pads and the test board of the present invention has a plurality of second contact pads and a plurality of test pads wherein all of the second contact pads are divided into a plurality of groups each connected to one pair of test pads, and all of the second contact pads in the same group are arranged in a line.
The first contact pads of the package substrate are adapted for receiving solder bumps. Selected pairs of the first contact pads are connected together to form a first daisy chain portion. Selected pairs of the second contact pads are connected together to form a second daisy chain portion. When the integrated circuit package is mounted on the test board with each solder bump soldered to a corresponding contact pad, all of the pairs of connected second contact pads and corresponding pairs of connected first contact pads form a conductive path (i.e., the “daisy chain”) that passes through all of the solder bumps therebetween.
According to the present invention, the testing method comprises the following steps: (a) mounting an integrated circuit package with the above mentioned substrate on the test board by reflowing solder bumps provided on the integrated circuit package to the second contact pads of the test board, and (b) performing an electrical test after conducting the mounting step.
In step (b), each group of connected second contact pads and corresponding connected first contact pads form a closed circuit through all of the older bumps therebetween when a corresponding pair of test pads are probed. Furthermore, the test board includes a pair of major test pads such that all of the second contact pads form a closed circuit when the pair of major test pads is probed.
It is noted that, when one pair of the test pads is probed, all of the second contact pads in the corresponding group are arranged in a line. Since the grinding operation of the SEM failure analysis is conducted from outer rows to inner rows, the time for conducting the SEM failure analysis is significantly reduced when the package substrate and the test board of the present invention are used.
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patent: 5840417 (1998-11-01), Bolger
patent: 6020633 (2000-02-01), Erickson
patent: 6040530 (2000-03-01), Wharton et al.
patent: 6075710 (2000-06-01), Lau
patent: 6121554 (2000-09-01), Kamikawa
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patent: 6483329 (2002-11-01), Cram
patent: 6535005 (2003-03-01), Field
patent: 6564986 (2003-05-01), Hsieh
Cheng Po Jen
Kung Heng Yu
Lee Chiu Wen
Lee Jin Zhu
Advanced Semiconductor Engineering Inc.
Hollington Jermele
Karlsen Ernest
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