Power-up circuit

Details Power-up circuit Power-up circuit

2002-12-30

2004-05-04

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

Reexamination Certificate

active

06731143

ABSTRACT:

BACKGROUND
1. Technical Field
A power-up circuit is disclosed which sets an initializing voltage so that the circuit can be normally driven at a time point when the power is on.
2. Description of the Related Art
Initialization and power-up circuits have been employed to reduce power consumption in semiconductor circuitry. However, currently available initialization and power-up circuits are not without their problems.
For example, an initializing circuit serves to keep a desired voltage at a node of the circuit for which initialization is required until the supply voltage reaches a specific voltage. However, if the supply power itself is low, there is a possibility that an initialization process may need to be repeated in the circuit because of power noise, etc.
FIG. 1
a
and
FIG. 1
b
show an operation principle of a conventional power-up circuit.
FIG. 1
a
and
FIG. 1
b
respectively show an initialization state and a state where initialization is completed.
When the power is on, the power reaches the supply voltage level within a short period of time. It can be seen that the power is increased at a given rate over a very short time unit.
FIG. 1
c
shows the power curve against time. In
FIG. 1
c
, a dotted line corresponds to the power curve when the power is on. Also, a solid line shows the voltage of the power-up node (PWRUP) in
FIG. 1
a.
Let us divide the operation of the power-up circuit into three regions. A first region is one where the voltage of the power-up node (PWRUP) is increased while the power is increased. This corresponds to a region before t
1
in
FIG. 1
c
. The reason why this region exists is that the PMOS transistor P
1
in
FIG. 1
a
is not turned on. A second region is one where the voltage a between the gate and source of the PMOS transistor P
1
is sufficiently increased and a VDD value (logically HIGI value) is thus transferred to a node X. At this time, the power-up node (PWRUP) logically has a LOW value. This corresponds to the region between t
1
and t
2
in
FIG. 1
c
. A third region is one where as the power is increased, the voltage of a node B in
FIG. 1
b
is increased and a NMOS transistor N
1
is turned on. At this time, the node X is discharged to logically have a LOW value and the power-up node (PWRUP) becomes logically HIGH. The voltage of the power-up node (PWRUP) after this region is same to the VDD voltage and the power-up is completed.
FIG. 2
represents problems in the existing power-up circuit occurring at a low-power condition. In detail,
FIG. 2
shows a correlation between power noise and the power-up level.
If noise exists in VDD under the low-power condition, it can be seen there is a possibility that the power-up level may be affected. By referring again to
FIG. 1
b
, when the voltage of the node B is lowered due to power noise, the NMOS transistor N
1
may not be sufficiently turned on. In this case, there is a significant problem that initialization can repeat itself since the power-up node (PWRUP) has a LOW value instantaneously. The possibility that this problem may occur is small as the difference between the VDD level and the power-up level is large. Thus, this is not a significant subject to be considered in the existing power-up circuit. However, as the VDD level is increasingly low, this problem becomes a subject that is necessarily considered.
SUMMARY OF THE DISCLOSURE
To solve the above problems, a power-up circuit is disclosed which is capable of preventing erroneous operation that may occur in an initialization process for a circuit that operates under a low-power condition.
A power-up circuit is also disclosed that can be applied to simple circuit systems and general VLSI systems.
A disclosed power-up circuit comprises a first PMOS transistor connected between the power supply and a first node, wherein a gate terminal of the first PMOS transistor is connected to the ground, a first voltage divider for dividing the power upon a power up, a first NMOS transistor driven an output of the first voltage divider upon a power up and connected between the first node and the ground, an inverter having a plurality of PMOS transistors connected between the power supply and a second node, in which gate electrodes of the plurality of inverter are connected from each other and a second NMOS transistor connected between the second node and the ground and gate of the second NMOS transistor is connected to the plurality of the PMOS transistors, thereby inverting the potential of the first node, and a third NMOS transistor connected between the first node and the ground, wherein the third NMOS transistor is turned on by an output of the inverter, thereby preventing shifting faster than the potential of the first node.


REFERENCES:
patent: 5166546 (1992-11-01), Savignac et al.
patent: 5612641 (1997-03-01), Sali
patent: 5825220 (1998-10-01), Kinugasa et al.
patent: 6469552 (2002-10-01), Ohbayashi et al.

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