Memory with address management

Details Memory with address management Memory with address management

2002-03-19

2004-09-28

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S230010, C365S230060, C365S233100

Reexamination Certificate

active

06798711

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to memory devices and in particular the present invention relates to address circuitry for memory devices.
BACKGROUND OF THE INVENTION
Memory devices are widely used in processing systems and consumer products. One type of memory device is a dynamic random access memory. Various kinds of DRAMs are commonly used. Typical examples are the synchronous DRAM (SDRAM) in which data is stored or retrieved in synchronism with a system clock and a double-data-rate SDRAM (DDR-SDRAM) which makes it possible to use both edges of a clock pulse as triggers for data access. In addition to the above described DRAMs, a RAMBUS DRAM (RDRAM) (under specifications of Rambus Inc.) in which data transfer is enabled at a high speed with a protocol-based command, and the like have also been developed.
Three prominent trends in memory design and manufacturing have been the reduction in component size, reduced operating power levels and the increase in operating speed. These three trends are interrelated and often adversely affect each other. For example, component size reductions are necessary to achieve desired memory storage density without significant increases in die size. The reduction in component size can increase communication line resistances, which result in slower operating speeds and increased power consumption.
All memory devices use an addressing scheme to access memory cells, or locations. Specifically, many memory devices have memory cell arrays that are arranged in multiple banks of rows and columns. External address input connections are used to provide the bank, row and column addresses. These addresses are usually buffered and routed to different locations of the memory device.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory device address management system that allows for reduced power consumption.
SUMMARY OF THE INVENTION
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a memory device comprises an address input connection, address buffer circuitry coupled to the address input connection to provide an address signal output on a buffer output in response to an input address signal, internal circuitry coupled to receive the address signal output, and control circuitry coupled to selectively allow the address signal output to be transmitted to the internal circuitry.
In another embodiment, a dynamic random access memory (DRAM) comprises a plurality of address input connections to receive externally provided bank, row and column addresses, and a plurality of internal address communication lines coupled to receive the bank, row and column addresses. A plurality of driver circuits are coupled to the plurality of internal address communication lines to drive the bank, row and column addresses on the plurality of internal address communication lines. Enable circuitry is coupled to control an input of the plurality of driver circuits to selectively enable the bank, row and column addresses to propagate on the plurality of internal address communication lines.
A method of operating a memory device comprises receiving externally provided control signals to instruct the memory to perform a selected function, receiving externally provided address signals, and prohibiting selected ones of the address signals from propagating through internal memory device circuitry based upon the selected function.
A method of operating a DRAM comprises receiving externally provided control signals to instruct the memory to perform a Read, Write, Active, or NOP (no operation) function, receiving externally provided row, column and bank address signals, and prohibiting selected ones of the row, column and bank address signals from propagating through internal DRAM address buses based upon a selected function.


REFERENCES:
patent: 4141068 (1979-02-01), Mager et al.
patent: 4509115 (1985-04-01), Manton et al.
patent: 4870619 (1989-09-01), Van Ness
patent: 4924427 (1990-05-01), Savage et al.
patent: RE35825 (1998-06-01), Zagar
patent: 5778446 (1998-07-01), Kim
patent: 5883855 (1999-03-01), Fujita
patent: 5898639 (1999-04-01), Blodgett
patent: RE36264 (1999-08-01), Merritt et al.
patent: 5999480 (1999-12-01), Ong et al.
patent: 6111797 (2000-08-01), Shirley
patent: 6147925 (2000-11-01), Tomishima et al.
patent: 6163489 (2000-12-01), Blodgett
patent: 6321316 (2001-11-01), Manning
patent: 6356500 (2002-03-01), Cloud et al.
patent: 6438055 (2002-08-01), Taguchi et al.
patent: 6466499 (2002-10-01), Blodgett
patent: 6473358 (2002-10-01), Noda et al.
patent: 6590822 (2003-07-01), Hwang et al.
patent: 2002/0064079 (2002-05-01), Sato et al.
patent: 2003/0088753 (2003-05-01), Ikeda et al.
patent: 356007162 (1981-01-01), None
patent: 363006637 (1988-01-01), None
patent: H4-131949 (1992-05-01), None
patent: 404131949 (1992-05-01), None

Affiliated with

Also associated with

Rating

Memory with address management does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory with address management, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory with address management will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3226543