Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2002-01-10
2004-07-20
Williams, Alexander Oscar (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S700000, C257S701000, C257S774000, C257S775000, C257S776000, C257S786000, C257S784000, C257S207000, C257S211000, C257S208000, C257S210000, C257S797000
Reexamination Certificate
active
06765296
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to vias in integrated circuits and more particularly to the via-sea connecting wide bottom metal and top metal conductors in integrated circuits.
BACKGROUND ART
In integrated circuits, interconnect structures generally take the form of patterned metalization lines, or wires, that are used to electrically interconnect individual semiconductor devices to external circuitry. The individual devices may include complimentary metal oxide semiconductor (CMOS) transistors and a single integrated circuit chip may include thousands or millions of such devices. These devices are powered by a power strip, or power line which is one of the top layers of an integrated circuit.
Generally, the devices are formed on a semiconductor substrate in a silicon wafer and then covered by a dielectric layer of a material such as silicon dioxide. Contacts are formed through the dielectric layer using photolithographic processes which include depositing a photoresist layer over the dielectric layer, selectively exposing the photoresist to light through a patterned reticle having contact hole patterns, developing the photoresist to form a photoresist contact mask, and etching the exposed dielectric layer to form the contact holes that lead to the devices. Once the contact holes are formed, a conductive material, such as tungsten, is used to fill the contact holes to form “tungsten plugs”. Additional dielectric layers are then deposited and similar photolithographic processes are used to form metalization layers and vias, which interconnect the metalization layers.
While contacts and vias in the lower levels form individual connections between the various metal lines, it has been found that a plurality of vias are required to connect to the power line. However, metal explosions, or metal voids, starting from the bottom of the vias extending upwards toward the top power line have been discovered. These metal explosions reduce the power carrying capability of the power lines and adversely affect the performance of the devices in the integrated circuit.
The reasons for this problem are poorly understood and a solution has long been sought but has equally long eluded those skilled in the art.
DISCLOSURE OF THE INVENTION
The present invention provides an integrated circuit interconnect having a wide top metal line and a wide bottom metal line. A dielectric layer is disposed between the wide top and wide bottom metal lines. A via-sea, including a first via having a width and a second via having a width and spaced more than a width away and less than four widths away from the first via in the dielectric layer, connects the wide top and wide bottom metal lines. The width and spacing of the vias reduce the occurrence of metal explosions which are known to reduce the power carrying capability of the power lines and adversely affect the performance of the devices in the integrated circuit.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.
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Chua Thow Phock
Lee Hong Lim
Park Jae Soo
Subramanyam Chivukula
Chartered Semiconductor Manufacturing Ltd.
Ishimaru Mikio
Williams Alexander Oscar
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