Electrical connectors – Preformed panel circuit arrangement – e.g. – pcb – icm – dip,... – With provision to conduct electricity from panel circuit to...
Reexamination Certificate
2003-01-17
2004-03-16
Gushi, Ross (Department: 2833)
Electrical connectors
Preformed panel circuit arrangement, e.g., pcb, icm, dip,...
With provision to conduct electricity from panel circuit to...
C356S052000, C257S686000
Reexamination Certificate
active
06705877
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to high input/output (I/O), high density, low cost electronic modules and, more particularly, to the high I/O, high density, high capacity, low cost packaging of high performance, high capacity memory devices such as Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) and having impedance-controlled buses for maintaining high electrical performance.
BACKGROUND OF THE INVENTION
In data processing and network systems, it is always a certainty that the demand in memory throughput will increase at a high rate. In recent years such increase has taken on a new dimension. While the demand for memory throughput has increased, the area available for mounted memory devices, the high quantities of I/O they require, and the height available has become increasingly restricted.
The Electronic Industries Association (EIA) has set up a standard for the dimensions for rack-mountable equipment. Traditionally, a piece of rack-mountable equipment has a standard width of 19 inches and a height in increments of 1.75 inches. This is also known as “1U”. However, a trend has begun to reduce the height for the servers in a server rack to dimensions appreciably lower than 1U.
This equipment height restriction has also placed height restrictions on other components such as memory modules. The traditional SDRAM dual inline memory modules (DIMMs) are simply too high to be able to be mounted vertically on the system board. Special sockets have been designed to allow DIMMs to be mounted either at an angle or even parallel to the system board.
One way to increase memory throughput is to increase the operating frequency of the memory devices. But this also requires the memory modules and connectors to support the higher speeds, which is becoming increasingly difficult to implement. Another way to increase memory throughput is to increase the bandwidth of the memory channel.
A 256-bit memory channel has four times the throughput of a 64-bit channel when operated at the same frequency. A higher throughput is important in many industries that run real-time applications (e.g., gaming, video graphics, speech processing, and networking applications). Increasing throughput through widening the bus is often much easier to implement and less expensive than methods such as doubling the clock frequency of the memory subsystem, reducing latency in bus cycles, and implementing complex multi-symbol modulation schemes or pulse code modulation (PCM) type approaches.
Increasing the throughput through widening the memory channel requires a significant increase in the quantity of I/O connections to support these memory devices while still trying to minimize the area used. This precludes the use of edge-interconnected memory modules such as traditional memory module form factors such as DIMMs and RAMBUS® Inline Memory Modules (RIMMs) and forces one to explore the use of area array interconnections. In some applications the interconnection is permanent (i.e., soldered) through a technique known as ball grid array (BGA) attachment, while others are field separable through pin grid array (PGA) and land grid array connectors.
BGA interconnections are viable for a quantity of up to approximately 1000 I/O. The mechanical reliability of larger BGA arrays is a concern due to the larger distance from neutral point (DNP) of the array, which is caused by coefficient of thermal expansion (CTE) mismatches. Moreover, manufacturability due to the nonplanarity of mating surfaces is also a concern.
PGA connectors are viable for field separable applications requiring a quantity of up to about 500 I/O. The mechanical reliability of larger surface mount PGA arrays is also a concern due to the larger distance from DNP of the array, which is caused by CTE mismatches.
For field separable applications requiring greater than 500 I/O, and grid array (LGA) connectors, and in particular LGA connectors as taught in some of the referenced copending U.S. patent applications, provide improved performance, increased density, lower height, and a CTE that better matches that of the surrounding structures.
One method being used today to solve the need to increase both memory capacity and density is to stack two, thin small outline package (TSOP) SDRAM devices on top of each other on a DIMM. An alternate approach is to stack two devices within a chip scale package (CSP). These stacking schemes, while increasing memory density, are not easily reworkable.
It is desirable to find a packaging solution that resolves the memory throughput capacity and density, interconnection quantity and density, and the height issues. In addition, the solution must also be low in cost, readily manufacturable, upgradeable with ample granularity, have improved electrical performance even at high frequencies, and have good reliability. Ample granularity allows the throughput on a given memory module to be increased or decreased as required (e.g., in increments of 16 bits, instead of 64 bits).
It is therefore an object of the invention to provide a variable bandwidth, high density, low profile SDRAM memory module for high performance memory devices.
It is another object of the invention to provide a variable bandwidth, high density, low profile SDRAM memory module that is readily manufacturable and upgradeable.
It is still another object of the invention to provide a variable bandwidth, high density, low profile SDRAM memory module that provides improved electrical performance at high frequencies and good reliability.
SUMMARY OF THE INVENTION
The present invention relates to a family of specialized embodiments of the modules taught in the referenced copending U.S. patent applications. A memory module is desired with granularity and upgradeability of bandwidth, and a low profile using 256 MB SDRAM or DDR SDRAM memory devices in CSPs to support a memory data bus width of up to at least 512 bits.
Each module includes a substrate, having contact pads and memory devices on its surfaces, and impedance-controlled transmission line signal paths. The substrates may be conventional printed circuit cards preferably with CSP packaged memory devices along with other components attached directly to both sides of the substrates.
The inclusion of spaced, multiple area array interconnections allows a row of memory devices to be symmetrically mounted on each side of each of the area array interconnections, thereby reducing the interconnect lengths and facilitating matching of interconnect lengths. The footprints for the interconnections between the substrates and to the system board are the same to reduce part number and reliability and qualification testing. Short area array interconnections, including BGA and LGA options provide interconnections between modules and the rest of the system. The distance between the spaced multiple area array interconnections is preferably chosen to ensure that the solder joints in the BGA interconnection option are reliable.
Driver line terminators may be included on the substrates for maintaining high electrical performance. Thermal control structures may also be included to maintain the memory devices within a reliable range of operating temperatures.
REFERENCES:
patent: 6172895 (2001-01-01), Brown et al.
patent: 6264476 (2001-07-01), Li et al.
patent: 6540525 (2003-04-01), Li et al.
patent: 6545895 (2003-04-01), Li et al.
U.S. patent application Ser. No. 09/932,654.
U.S. patent application Ser. No. 10/077,057, Moriarty et al.
Fan Zhineng
Li Che-yu
Moriarty Sharon Laura
Gushi Ross
High Connection Density Inc.
Nguyen Phuongchi
Salzman & Levy
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