Duty cycle correction circuit for use with frequency...

Details Duty cycle correction circuit for use with frequency... Duty cycle correction circuit for use with frequency...

2002-10-15

2004-05-18

Kinkead, Arnold (Department: 2817)

Oscillators

Combined with particular output coupling network

C331S00100A, C331S034000, C327S113000, C327S115000, C327S172000, C327S175000, C327S176000, C327S107000, C377S047000

Reexamination Certificate

active

06737927

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a duty cycle correction circuit, and more particularly to a duty cycle correction circuit for use with a frequency synthesizer.
BACKGROUND OF THE INVENTION
FIG.
1
(
a
) is a functional block diagram of a conventional frequency synthesizer. A control-voltage signal Vcntl is delivered from a control-voltage generating device
10
, which is composed of a phase detector (PD) or a phase-frequency detector (PFD)
11
, a charge pump
12
and a loop filter
13
, into a voltage-control oscillator (VCO)
14
. In accordance with the voltage level of the control-voltage signal Vcntl, the voltage-control oscillator (VCO)
14
delivers a pair of differential analog signals fp
0
and fp
180
into a differential-to-single-ended buffer circuit
15
. The differential analog signals fp
0
and fp
180
are converted into a single-ended signal and further amplified into a digital signal Fvco by means of the differential-to-single ended buffer circuit
15
. Such digital signal Fvco is fed back into the phase detector (PD) or the phase-frequency detector (PFD)
11
by a divided-by-N counter
17
to be compared with a reference frequency signal Fref and thus control the voltage level of the control-voltage signal Vcntl. Therefore, a digital signal Fvco with a stable waveform is obtained in accordance with the relation of Fvco=Fref×N.
FIGS. 2 and 3
are respectively circuit diagrams of the voltage-control oscillator
14
and the differential-to-single-ended buffer circuit
15
. The voltage-control oscillator
14
includes three delay circuits DELAY
1
, DELAY
2
and DELAY
3
for processing the control-voltage signal Vcntl and thus outputting the pair of differential analog signals fp
0
and fp
180
. The differential-to-single-ended buffer circuit
15
is implemented by employing four MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), i.e. MN
1
, MN
2
, MP
1
and MP
2
, and two inverters, i.e. INV
1
and INV
2
. The operation and principle of the differential-to-single-ended buffer circuit
15
are well known in the art and need not be further described in details herein. Since the loads on the drain terminals MN
1
and MN
2
are asymmetrical, the duty cycle would possibly be distorted. In addition, the bandwidth of the differential-to-single-ended buffer circuit
15
might vary with the extrinsic parameters, for example device processing temperature, voltage and/or frequency of the frequency synthesizer, the variation of which also distorts the duty cycle. Especially when the frequency synthesizer is operated at different frequencies, the duty cycle distortion is beyond control. For example, the data transfer rate of a CD-ROM/DVD-ROM read-out circuit for the radially outer portion of a disc is approximately 2.5 times as large as that for the radially inner portion. Therefore, the duty cycle distortion occurs due to the frequency difference in the same oscillator. For the above reasons, it is difficult to effectively maintain the duty cycle of the digital signal Fvco at 50%.
The distortion of the duty cycle of the digital signal Fvco away from 50% will result in a poor bit-error rate and an inferior lock-in range of a clock and data recovery circuit, and is thus required to be improved. The prior art with reference to FIG.
1
(
a
) uses a divide-by-two circuit
16
connected with the differential-to-single-ended buffer circuit
15
to solve this problem. By dividing the frequency of the digital signal Fvco by two, the duty cycle distortion can be disregarded, and a pulse signal CLKO of a duty cycle 50% is obtained, as shown in FIG.
1
(
b
).
However, the circuit configuration of the above frequency synthesizer has some disadvantages. For example, the frequency of the digital signal Fvco has to double in advance in order to obtain the pulse signal CLKO of a desired frequency. Thus, the power consumption of the frequency synthesizer and the complexity of the divide-by-two circuit
16
are increased. This disadvantage is apparent especially when the working frequency of the current central processing unit (CPU) is as high as several gigahertz.
SUMMARY OF THE INVENTION
Therefore, the present invention provides a duty cycle correction circuit for use with a frequency synthesizer, which facilitates reducing power consumption and circuit complexity and still allows the output pulse signal to be fixed at a 50% duty cycle.
In accordance with an aspect of the present invention, there is provided a duty cycle correction circuit for converting a pair of differential analog signals from an oscillator into an output pulse signal with 50% of duty cycle. The pulse signal has the same frequency as that of each of the differential analog signals. The duty cycle correction circuit includes a first differential-to-single-ended buffer circuit, a second differential-to-single-ended buffer circuit, a first frequency divider, a second frequency divider and a symmetrical exclusive OR element. The first differential-to-single-ended buffer circuit is used for processing the pair of differential analog signals into a first digital pulse signal. The second differential-to-single-ended buffer circuit is used for processing the pair of differential analog signals into a second digital pulse signal, wherein the first digital pulse signal and the second digital pulse signal have a specified phase difference therebetween. The first frequency divider is electrically connected with the first differential-to-single-ended buffer circuit for frequency-dividing the first digital pulse signal into a third digital pulse signal. The second frequency divider is electrically connected with the second differential-to-single-ended buffer circuit for frequency-dividing the second digital pulse signal into a fourth digital pulse signal. The symmetrical exclusive OR element is electrically connected with the first frequency divider and the second frequency divider for performing an exclusive OR operation so as to produce the output pulse signal.
In an embodiment, the specified phase difference is 180 degrees. The first frequency divider and the second frequency divider respectively include a first divide-by-two circuit and a second divide-by-two circuit.
For example, the symmetrical exclusive OR element includes a first inverter, a second inverter, a first NAND gate, a second NAND gate, and a third NAND gate. An output end of the first inverter is electrically connected with a first input end of the first NAND gate, an output end of the second inverter is electrically connected with a first input end of the second NAND gate, and an output end of the first NAND gate and an output end of the second NAND gate are respectively connected with a first input end and a second input end of the third NAND gate. The third digital pulse signal is inputted into the first inverter and a second input end of the second NAND gate, and the fourth digital pulse signal is inputted into the second inverter and a second input end of the first NAND gate.
Preferably, the third NAND gate is a symmetrical NAND gate. In an embodiment, the third NAND gate is implemented by a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor, the first PMOS transistor is connected with the first NMOS transistor and the second NMOS transistor in series, the second PMOS transistor is connected with the third NMOS transistor and the fourth NMOS transistor in series, the source terminals of the first PMOS transistor and the second PMOS transistor are connected to a power supply voltage, and the source terminals of the second NMOS transistor and the fourth NMOS transistor are grounded. The gate terminals of the first PMOS transistor, the first NMOS transistor and the fourth NMOS transistor are interconnected to form the first input end of the third NAND gate. The gate terminals of the second PMOS transistor, the second NMOS transistor and the third NMOS transistor are interconnected to form the second input end of the

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