Semiconductor device array having dense memory cell array...

Details Semiconductor device array having dense memory cell array... Semiconductor device array having dense memory cell array...

2003-05-02

2004-07-27

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S202000, C365S189080, C365S214000, C365S207000, C365S231000

Reexamination Certificate

active

06768663

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductor memory devices, and more particularly to the memory cell arrays and surrounding circuitry of semiconductor memory devices.
BACKGROUND OF THE INVENTION
The increased computing power of each generation of electronic systems has given rise to the need for semiconductor memory devices of greater and greater storage density. Storage density refers the amount of data that can be stored in a given area on a semiconductor substrate. Because integrated circuits are typically manufactured by forming multiple die on a semiconductor wafer, in general, the higher the density of the design, the more economical it is to produce the integrated circuit. This can apply not only to “standalone” semiconductor memory devices (those devices whose only function is the storage of data), but also to devices having “embedded” memory as well. Embedded memory is a section of memory that is included on a larger integrated circuit. Embedded higher density semiconductor memory designs also free up more area on the larger integrated circuit, allowing for greater flexibility in design and/or added features.
A preferred type of semiconductor memory device, due to its high density and relatively low power consumption characteristics, is the dynamic random access memory (DRAM). Because of this, any practical approaches to improving DRAM density could benefit a great number of electronic systems.
Conventional DRAM architectures are well known. A DRAM will typically include an array of memory cells that are coupled to bit lines by the activation of word lines. The DRAM will further include a number of sense amplifiers, each of which amplifies a differential signal at its two inputs. The inputs of each sense amplifier are coupled to bit lines, and in any active operation, one input will be coupled to a bit line carrying a data signal while the other input will be coupled to a reference signal. A data signal that is greater than the reference signal will be amplified to generate one logic value (a logic “1” for example), while a data signal that is less than the reference signal will be amplified to generate another logic value (a logic “0” for example).
DRAMs architectures include “open” bit line architectures as well as “folded” bit line architectures. Typical open bit line architectures are utilized in dense memory cell arrangements, where the activation of a word line results in data being placed on adjacent bit lines. In such applications the reference signal is often generated by a “dummy” memory cell. A drawback to open bit line architectures is the susceptibility of such architectures to noise. Such noise can limit the size of the bit lines or cell capacitors, and/or require additional sense amplifiers.
For this reason, open bit line architectures are usually avoided.
Folded bit line architectures reduce the adverse effects of noise. In a folded bit line architecture, adjacent bit lines each form a folded bit line pair. Each folded bit line pair is coupled as the inputs to a differential-type sense amplifier. When a word line is activated, data is placed on one bit line of the bit line pair but not on the other bit line of the bit line pair. This allows the adjacent bit line to carry a reference signal. By using adjacent bit lines (which have the same general dimensions and are made of the same material) the majority of the noise will be common mode noise, and can be rejected by the sense amplifier.
An example of a prior art folded bit line DRAM memory array arrangement is set forth in
FIGS. 1A-1E
. The prior art folded bit line DRAM array is composed of a number of memory cells, two of which are set forth in FIG.
1
A. The memory cells are designated by the general reference characters
100
a
and
100
b
, and in the view of
FIG. 1A
, are shown to be formed in an active area
102
that is surrounded by an insulation region
104
. Each of the memory cells (
100
a
and
100
b
) includes an associated word line (
106
a
and
106
b
) created over the active area
102
to thereby form a metal-oxide-semiconductor (MOS) transistor. The memory cells (
100
a
and
100
b
) share a common bit line contact
108
that is formed between the word lines (
106
a
and
106
b
).
The memory cells (
100
a
and
100
b
) set forth in
FIG. 1A
are often referred to as “8F
2
” memory cells, because of the area occupied by each memory cell. For a given semiconductor device manufacturing process, given a minimum feature size, shown as “F,” the area formed by each memory cell is a rectangle having sides of 4F and 2F. The memory cell pair (
100
a
and
100
b
) will thus occupy 16F
2
.
To assist in understanding the arrangement of the various embodiments set forth herein, a prior art memory cell array utilizing 8F
2
memory cells will be described in a series of top plan views in
FIGS. 1B
to
1
E.
FIGS. 1B
to
1
E all set forth a portion of a DRAM array with the area of memory cell pairs being delineated with a bold dashed line. Each view illustrates a different set of layers.
FIG. 1B
illustrates the word lines (
110
a
-
110
h
) and bit line contacts as set forth in FIG.
1
A. Only selected of the bit line contacts are identified by the reference character
112
to avoid cluttering the view of FIG.
1
B. In addition, storage node contacts for each memory cell are also set forth. For the same reasons, only selected of the storage contacts are identified by the reference character
114
. The storage node contacts
114
connect the transistors formed within the substrate to storage capacitors that are disposed above the substrate. The bit lines contacts
112
connect bit lines to the substrate.
FIG. 1C
is a top plan view illustrating additional layers formed on top of those set forth in FIG.
1
B. Included are local bit lines (
116
a
-
116
c
) and storage nodes. Selected storage nodes are shown as items
118
. In addition, for reference, the bit line contacts
112
have been carried over from FIG.
1
B. The storage node arrangement of
FIG. 1C
describes a “capacitor-under-bit line” (CUB) arrangement. Thus, prior to the formation of the bit line contacts
112
, the storage nodes
118
are formed. It is understood that the storage nodes
118
function as one plate of a storage capacitor. Accordingly, subsequent to their formation, a capacitor dielectric will be formed over the storage nodes
118
, which will then be covered by a capacitor plate common to all of the storage capacitors.
The local bit lines (
116
a
-
116
c
) of
FIG. 1C
are shown to extend over the substrate, perpendicular to the word lines (
110
a
-
110
h
). The local bit lines (
116
a
-
116
c
) make contact to each of the memory cell pairs at the corresponding the bit line contacts
112
.
FIG. 1D
is the same top plan view as
FIG. 1C
, but illustrates a different capacitor configuration. Instead of a CUB type arrangement,
FIG. 1C
illustrates the case of a capacitor-over-bit line (COB) arrangement. Thus, while
FIG. 1D
includes the same bit line (
116
a
-
116
c
) and bit line contact
112
arrangement, COB type storage nodes, selected of which are shown as items
120
are also set forth. As in the case of
FIG. 1C
, a capacitor dielectric and a common plate are formed over the storage nodes
120
.
FIG. 1E
illustrates how a “global” bit lines (
122
a
-
122
c
) are formed over the local bit lines (
116
a
-
116
c
). The “global” bit lines (
122
a
-
122
c
) are typically made from a lower resistance material than the local bit lines (
116
a
-
116
c
). Data signals on the local bit lines (
116
a
-
116
c
) may be coupled to corresponding global bit lines (
122
a
-
122
c
) by way of bit line select circuits (not shown in FIGS.
1
A-
1
E).
FIGS. 1A-1E
can also be instructive to illustrate additional concerns that arise in the manufacture of integrated circuits. If the conductive layers required to form the storage capacitors (i.e., the storage node and the common plate) are discounted, three conductive layers are required to form the memory cell array. The first conductive layer forms the word

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