Semiconductor integrated circuit device and data...

Details Semiconductor integrated circuit device and data... Semiconductor integrated circuit device and data...

2003-03-04

2004-04-27

Wamsley, Patrick (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

C326S093000

Reexamination Certificate

active

06727831

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and a data/signal transmission system, and in particular to a device and a system where data or signals which are transmitted/received among a plurality of semiconductor integrated circuits are handled as current amounts, and which are used, for example, in a transmission system connected with a semiconductor memory and a controller therefor.
A conventional transmission system which connects a plurality of LSIs handles voltage potentials as data. For example, a conventional transmission system which is connected with a semiconductor memory and a controller therefor is configured as shown in
FIG. 56
or FIG.
57
.
The conventional data transmission system generally illustrated in
FIG. 56
comprises a plurality of synchronous dynamic memories (SDRAM)
421
arranged in a two-dimensional array, and a common memory controller
420
. The illustrated data transmission system also comprises a clock/address bus
422
which connects the common memory controller
420
to each of the SDRAMs
421
for supplying a clock signal Clock and an address signal Address from the memory controller
420
to the SDRAM
421
; a data bus
423
which connects the memory controller
420
to the respective rows of the SDRAMS
421
for transmitting data DATA to corresponding SDRAMS in the respective rows; and a control signal bus
424
which connects the common memory controller
420
to the respective columns of the SDRAMs
421
for supplying corresponding DRAMs
421
in the respective columns with control signals (RAS#
1
, CAS#
1
, WE#
1
, CS#
1
)-(RAS#
4
, CAS#
4
, WE#
4
, CS#).
A memory module comprised of the plurality of SDRAMs
421
arranged in a two-dimensional array on a printed circuit board can save the bus width of data and accordingly transmit a large amount of data on a relatively low speed bus.
However, the data transmission system illustrated in
FIG. 56
has a problem of a large number of wires required for the bus, and a problem of reflection noise being readily introduced into the bus due to the unterminated bus leading to the inability of accomplishing faster data reading. In addition, since the control signal bus, the address bus and the data bus are inconsistent in load, the timing of setup/hold time varies among respective signals in each SDRAM depending on the distance from the memory control to each SDRAM.
Since this results in failure in reducing a timing margin in each SDRAM, each SDRAM cannot operate at a higher rate. Therefore, an attempt of increasing the data transfer rate must rely on an increase in bus width, causing difficulties in the layout of the memory module and in ensuring the consistency in load among respective signals.
A conventional data transmission system illustrated in
FIG. 57
, on the other hand, interconnects a plurality of Rambus type DRAMs (RDRAMs)
331
through a Rambus channel (proposed by Rambus Co.) which is a one-dimensional data transmission path, and connects a memory controller
330
between the Rambus channel and an external bus, such that a reference potential Vref and a synchronization clock CTM from a clock signal source
332
are supplied to the respective DRAMs
331
through the Rambus channel. Incidentally, the above Rambus channel is terminated through a terminal resistance
333
so as not to generate reflection noises, and loads of respective buses are made uniform in order to suppress occurrence of a skew between transmission signals of a bus.
A memory module comprised of the plurality of DRAM
331
arranged in a one-dimensional array on a printed circuit board as mentioned can simplify the bus configuration, and provides a faster synchronization clock to transmit/receive a large amount of data.
The data transmission system illustrated in
FIG. 57
, however, speeds up the transmission/reception of data at the sacrifice of an increase in the bus width, so that the data transmission system requires tight specifications for the skew between the buses in the overall memory module and limited jitter for a clock driver. To meet the requirements, it is necessary to precisely control the resistance, inductance, and inter-wire mutual inductance of wires on the printed circuit board of the memory module, resulting in a higher cost.
In addition, the miniaturization of elements in LSI inevitably requires a lower power supply voltage for outputting (ex.
FIG. 56
) and a lower terminal voltage VTERM of the bus (ex.
FIG. 57
) in consideration of the breakdown of transistors within LSIs in a memory module. This results in a reduced voltage amplitude of the data, causing a higher susceptibility to erroneous reading of data.
As described above, the conventional data transmission system which handles a large amount of data with a relatively low speed bus suffers from a large number of bus wires and the inability of speeding up the data read.
On the other hand, the conventional data transmission system which simplifies the bus configuration and speeds up the synchronization clock to transmit/receive a large amount of data requires tight specifications for the skew between the buses in the overall memory module and limited jitter for a clock driver, and accordingly entails a higher cost for meeting the requirements. The susceptibility to erroneously read data due to a reduced amplitude of the data can occur because of lowering the power supply voltage for output (ex.
FIG. 56
) and the terminal voltage (ex.
FIG. 57
) in consideration of the breakdown of transistors within LSIs in a memory module.
BRIEF SUMMARY OF THE INVENTION
The present invention has been made to solve the problems mentioned above, and it is an object of the present invention to provide a data transmission system which is capable of avoiding the problem which may arise when a voltage potential is handled as transmission data by handling current amounts as transmission data, and a semiconductor integrated circuit device which is adapted to this data transmission system.
It is another object of the present invention to provide a semiconductor integrated circuit device which is capable of transmitting multi-value data without entailing an increase in transmission data width by representing current data in multi-value form, providing a wider voltage noise margin, readily accommodating a reduction in a power supply voltage and an amplitude voltage on an external signal line resulting from the miniaturization of LSI devices, and transmitting/receiving a large amount of data even when a low speed synchronization clock is transmitted, and a data transmission system using the semiconductor integrated circuit device.
According to an aspect of the present invention, a data transmission system is provided including a clock source, a plurality of semiconductor integrated circuit devices, a controller configured to control the plurality of semiconductor integrated circuit devices, and a clock signal pass connected to the clock source, the controller and the plurality of semiconductor integrated circuit devices.
In one further aspect, the data transmission system may further include a daisy chain data pass connected to the controller and the plurality of semiconductor integrated circuit devices, and a two-way data strobe signal pass connected to the controller and the plurality of semiconductor integrated circuit devices. According to this aspect, the clock source, the plurality of semiconductor integrated circuit devices and the controller transmit and receive therebetween a clock signal via the clock signal pass, the plurality of semiconductor integrated circuit devices and the controller transmit and receive therebetween multi-valued current data via the daisy chain data pass, and the plurality of semiconductor integrated circuit devices and the controller transmit and receive therebetween a data strobe signal in the form of a binary voltage signal via the two-way data strobe signal pass.
In another further aspect, the data transmission system may further include a

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