Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2003-05-30
2004-09-21
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S208000, C327S210000
Reexamination Certificate
active
06794916
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to double edge-triggered flip-flops.
BACKGROUND
Flip-flops are a basic element of digital memory. To reduce the complexity of circuit to designs, a large proportion of digital circuits are synchronous in the sense that they operate using a clock. A flip-flop is one such circuit. Flip-flops typically latch data either on the rising or the falling edge of the clock cycle. This arrangement is inefficient as half of the clock edges are wasted, while the full implemental cost of the entire clock is borne.
In S. H. Unger, June 1981, “Double Edge-triggered Flip-flops”,
IEEE Trans. Computers
, vol. C-30, no. 6, pp. 447-451, an attempt is proposed to overcome this above-mentioned inefficiency by using both the edges of the clock. The proposal is limited, however, by its complexity, which undercuts the gain made by the use of both clock edges. Still, this work prompted other attempts to simplify double edge-triggered (DET) flip-flops. As a general proposition, each of these attempts is responsible for reducing the overhead of DET flip-flops to more acceptable levels.
The use of weak transistors in feedback circuits of double-edge triggered flip-flop circuits is taught by G. M. Blair, “Low-power double-edge triggered flipflop”, in
Electronics Letters
, 8 May 1997, Vol. 33, No. 10, pp 845-847.
U.S. Pat. No. 6,310,500, issued Oct. 30, 2001 to Varma, describes resolving race conflicts between input and output nodes of a loop circuit (for example, a latch), and especially one adapted for use in the flip-flop circuits of a digital memory. In summary, this publication describes using clock skew-based race resolution within loops/latches.
A closely related teaching is given in P. Varma and K. N. Ramganesh, “Skewing Clock to Decide Races—Double-edge-triggered Flip-flop”,
Electronics Letters
, 6 Dec. 2001, Vol. 37, No. 25, pp 1506-1507.
U.S. Pat. No. 6,462,596, issued Oct. 8, 2002 to Varma, describes a static, double-edge triggered flip-flop having an upper data path and a lower data path connected between a data input node and an output terminal. The upper path includes a switch connected to a first data loop, and the lower path includes a switch connected to a second data loop. The first and second data loops share a forward path having a data-inverting circuit. In addition, each loop has a feedback path which contains only one element in the form of a switch.
Though various contributions have been made to the art of DET flip-flops, a need clearly exists for a design that still further improves the relative cost and performance of DET flip-flops.
SUMMARY
This need is achieved by a static, double-edge triggered flip-flop which has two bi-direction feedback paths connected from the output terminal to a respective intermediate node. One feedback path lies in a data path relating to the clock signal. The other feedback path lies in a data path relating to the complementary clock signal. The feedback paths each have a switch which operate on a skewed clock signal and complementary skewed clock signal, respectively.
The switches in the feedback paths can be weak transistors gated by the respective clock signals.
The DET flip-flop circuit designs disclosed herein use clock skew in parallel latches/loops, allowing inter-loop skew-driven interaction to improve the speed of race resolution for individual loops. Transistors are the only circuit elements used between an interconnection of input, clock, skewed clock, voltage supply, and output. Multiple loops, resolved individually by clock/phase skew, can assist each other's race resolution, by being organized in parallel and using bi-directional feedback paths.
The “nuisance value” of the initial period of a loop going out of phase, when a skewed phase feedback path is still active is turned into a beneficial advantage for inter-loop interaction. When multiple phase-skew-based loops share an output node then, as the phase shifts between the loops, the outgoing phase of one loop can benefit the incoming phase of another loop by biasing the shared output node in the direction of the incoming phase loop. Such a bias then assists the race resolution of the incoming phase loop.
Application of skew in flip-flop designs described herein yields an intra-loop power benefit in resolving races among the input/output nodes of the latches. Inter-loop interaction in the flip-flops arises when the trailing leg of the skewed clock in a “just disabled” latch leaves a still-enabled bi-directional feedback path touching the shared latch output.
This bi-directional path allows a temporary parallel data feedforward path to develop all the way from the flip-flop input to the shared output of the parallel latches comprising the flip-flops. This feedforward biases the shared output towards the voltage sought by a just enabled latch, which in turn speeds up the enabled latch's race settlement. Consequently, the operation of the flip-flop as a whole is improved.
The unshared paths in the outer loops are switched by the clock (or complementary clock), or skewed clock (or complementary, skewed clock). Accordingly, such a design is amenable to a low power implementation wherein the effect on power of threshold voltage drop due to an n-channel metal-oxide-semiconductor (NMOSFET, or NMOS) used as a pass transistor can be rectified by the pullup effect of a feedback p-channel MOS (PMOS) transistor.
The feedback paths of the outer loops use a skewed clock and extra resistance combination compared to the forward paths. High-speed, reduced-power operation across multiple voltages results is achieved, due to use of MOS-style clocked inverters, and the clock skew method of deciding races that also provides parallel feedforward.
MOSFETS can be used as the circuit elements. MOSFETS allow high-speed, reduced transistor, and low power complementary-symmetry MOS (CMOS) DET flip-flops, in which transistor gate area and switching capacitance is also reduced. Switching capacitance is proportional to the switched transistor gate area. Thus, when the switched gate area goes down, so does the capacitance.
Several designs are described in CMOS technology. CMOS flip-flops are widely used in building many systems including portable, handheld systems, personal computers, servers, etc. Thus reduced power and high-speed operation is possible. Cooling requirements are also reduced, battery life and device life are increased, and maintenance costs are reduced.
The DET flip-flop circuit designs described herein can be of mixed-mode circuit design. In a mixed-mode design, high-speed operations are delegated to the high-speed-oriented DET flip-flops described herein, enabling a reduction in clock speed. A mixture of SET and DET flip-flops can perform lower speed work. Clock speed requirements can be relaxed by using DET flip-flops to perform high-speed operations.
REFERENCES:
patent: 5081377 (1992-01-01), Freyman
patent: 6310500 (2001-10-01), Varma
patent: 6462596 (2002-10-01), Varma
S.H. Unger, “Double Edge-triggered flip-flops”, IEEE Trans. Computers. Jun. 1981, pp 447-451. vol. C-30, No. 6.
P. Varma and K.N. Ramganesh, “Skewing Clock to Decide Races—Double-edge-triggered Flip-flop”, Electronics Letters, Dec. 6, 2001, pp 1506-1507, vol. 37, No. 25.
G.M. Blair, “Low-power Double-edge Triggered Flipflop”, Electronics Letters, May 8, 1997, pp 845-847, vol. 33, No. 10.
Varma et al.,“A MOS Approach to CMOS DET FLip-Flop Design”, IEEE Transactions, vol. 49, No. 7, Jul. 2002, pp. 1013-1016.
Coca, Esq. T. Rao
International Business Machines - Corporation
Lam Tuan T.
McGinn & Gibb PLLC
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