Digital level shifter for maintaining gate oxide integrity...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control

Reexamination Certificate

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Details

C327S108000, C327S112000, C326S068000, C326S081000

Reexamination Certificate

active

06741115

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to voltage shifter circuits, and more particularly to a digital level shifter for maintaining gate oxide integrity of driver devices provided to interface external devices operating at elevated voltage levels, where the driver devices have been scaled to the extent that they cannot tolerate elevated-voltage inputs.
2. Description of the Related Art
As integrated circuit design and fabrication techniques have evolved over the years, the trend is that operating voltages have scaled downward along with device size. Very Large Scale Integrated (VLSI) circuits, particularly microprocessors, tend to lead in the area, of size and voltage scaling. As a result, VLSI devices which operate at lower voltages are required to interface to external devices, such as input/output (I/O) devices or the like, that have not been scaled to the same extent as the VLSI devices. Nonetheless, the external devices must be driven to voltage levels much higher than those of the VLSI device cores. As a result, many existing scaled VLSI devices provide voltage conversion circuits to increase the voltage swing of I/O signals so that they can properly interface to the elevated voltage external devices.
In more recent years, however, VLSI device sizes and operating voltages have decreased to the extent that, in some cases, scaled P-channel devices that provide an interface to elevated voltage external devices experience gate oxide breakdown if those same elevated voltage levels are used to drive their inputs. Because these P-channel devices have been significantly scaled, their gate oxide thickness is so thin that, if their gate is taken to the lowest voltage in the digital voltage range (e.g., 0 volts) while their source is tied to the elevated voltage (e.g., 3.3 volts), then the source-to-gate voltage V
SG
, the channel-to-gate voltage V
CG
, and the drain-to-gate voltage V
DG
, all exceed the breakdown voltage of the gate oxide, referred to as V
BROX
.
Voltage conversion circuits have heretofore been very simple because their only requirement has been to increase the level of a logic 1 (say, from 3.3 volts to 5 volts) while maintaining zero (0) volts as a logic zero level. However, conventional level shifting techniques are becoming clearly disadvantageous as silicon devices. continue to scale downward. For example, VLSI devices. today are fabricated using a 0.18 micron process that results in a gate oxide thickness of approximately 40 angstroms (Å) on a typical device. Skilled artisans will appreciate that the breakdown voltage for silicon dioxide (SiO
2
) is roughly 10
7
volts per centimeter (V/cm), and they also appreciate that it is prudent to restrict gate voltages to approximately 60 percent of the breakdown value. Hence, a prudent breakdown threshold, V
BROX
, for a 0.18 micron device is approximately 2.4 volts. The 0.18 micron devices are typically operated at VDD=1.8 volts referenced to ground at 0 volts, so that they generate a logic one (1) at 1.8 volts and a logic 0 at 0 volts. Thus, gate oxide breakdown at core voltage levels is not a problem. These devices, however, are typically required to interface to external Complementary Metal-Oxide Semiconductor (CMOS) devices that operate at higher voltage levels, such as 3.3 volts. As a result, pulling a 0.18 micron P-channel output device up to 3.3 volts, while holding its gate at zero volts will very likely damage the gate oxide of the P-channel device. Consequently, a traditional voltage conversion circuit will not work under these circumstances.
More recent techniques for output voltage scaling utilize both digital and analog circuits to shift a logic 1 at a core voltage level up to the elevated level of the external devices, and to shift a logic 0 from 0 volts up to an intermediate voltage level. The intermediate voltage level is chosen low enough to turn on a P-channel device, yet high enough to avoid breakdown of the gate oxide. The analog circuitry is employed to create a logic 0 bias for the digital circuits so that a logic 0 is established at the intermediate voltage level as opposed to 0 volts. Analog devices, however, tend to be physically large and power hungry, and these attributes make analog devices ill-suited for VLSI device applications.
Therefore, what is needed is to provide for control of scaled P-channel output driver devices which are subject to gate oxide breakdown because they have been scaled to the extent that their gate oxide layers are too thin to tolerate input signal levels at the same elevated levels which they are required to provide at their outputs.
SUMMARY OF THE INVENTION
A digital level shifter according to an embodiment of the present invention is provided to drive the input of a scaled driver device within a voltage shifted range to preclude gate-oxide breakdown of the scaled driver device. The scaled driver device has an output operative within an elevated voltage range, so that the voltage shifted range biases the voltage associated with a logic signal from a lower voltage level to an intermediate level to maintain the breakdown threshold and protect the scaled driver device. The digital level shifter is implemented using digital devices thereby avoiding analog bias devices. The digital level shifter and the scaled driver device may be implemented on the same integrated circuit (IC) and fabricated using the same process as core circuitry so that the IC may directly interface external devices operating at elevated voltage levels without damaging the core circuitry or the scaled driver device.
A digital level shifter according to an embodiment of the present invention includes a digital voltage limiter and a digital level-shifted switch. The digital voltage limiter is coupled to first and second source voltages having first and second voltage levels, respectively, defining a first voltage range. The digital voltage limiter receives a digital input signal operative within the first voltage range and provides a corresponding voltage limited signal operative within a limited voltage range between the second voltage level and an intermediate voltage level that has a magnitude between the first and second voltage levels. The intermediate voltage level is selected to prevent excessive input voltage to the scaled driver device. The digital level-shifted switch is coupled to a third source voltage and the first source voltage, where the third source voltage has a third voltage level magnitude that is greater than the second voltage level. The digital level-shifted switch receives the voltage limited signal and correspondingly switches a voltage shifted digital signal within a voltage shifted range defined between the intermediate and third voltage levels in response to switching of the voltage limited signal.
A digital level shifter according to another embodiment of the present invention includes a digital voltage divider and a digital level-shifted switch. The digital voltage divider includes P-channel devices coupled between a reference voltage and a first source voltage. The digital voltage divider receives a digital input signal operative within a first voltage range between the reference and first source voltages and has a junction that develops a voltage limited signal. The voltage limited signal is operative within a limited voltage range between the first source voltage and an intermediate voltage and has a voltage level between the reference voltage and the first source voltage. The digital level-shifted switch includes P-channel and N-channel devices coupled in a complementary configuration between the reference voltage and a second source voltage. The second source voltage has a voltage level that is greater than the first source voltage. The digital switch has an input that receives the voltage limited signal and an output that provides a shifted digital signal operative within a voltage shifted range between the intermediate and second source voltages.
An integrated circuit (IC) according to an embodiment of the pre

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