Electrical computers and digital processing systems: multicomput – Computer-to-computer data modifying – Compressing/decompressing
Reexamination Certificate
2000-05-18
2004-01-13
Vu, Viet D. (Department: 2154)
Electrical computers and digital processing systems: multicomput
Computer-to-computer data modifying
Compressing/decompressing
C714S033000, C714S036000
Reexamination Certificate
active
06678739
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to test pattern compression applicable to fault detection of logic circuits and more particularly, to a system, a method, and a computer program product for compressing a test pattern set, which is applicable to fault detection of logic circuits.
2. Description of the Related Art
A test pattern set used for fault detection of logic circuits includes redundant test patterns and thus, “test pattern set compression” has been usually employed to decrease the number of test patterns included in a test pattern set without lowering the fault coverage.
To perform the “test pattern set compression”, reverse order fault simulation, undefined value assignment to random numbers, and test pattern merging have ever been combined together and used. The reverse order fault simulation is as follows.
First, the initial order of test patterns included in a test pattern set for a logic circuit to be tested (i.e., a target logic circuit) is reversed, forming order-reversed test patterns in the set. Then, the operation of the target logic circuit is simulated using the order-reversed test patterns, specifying unnecessary test patterns in the set. Finally, the unnecessary patterns thus specified are removed or deleted from the set, resulting in compression of the set. The reverse order fault simulation is disclosed in, for example, a paper written by Michael H. Schultz et al., IEEE Trans. On CAD, pp. 126-137, January 1988, “SOCRATES: A HIGHLY EFFICIENT AUTOMATIC TEST PATTERN GENERATION SYSTEM”.
FIG. 1
is a functional block diagram showing a prior-art test pattern set generator having a test pattern set compression system
700
. The test pattern set generator in
FIG. 1
comprises circuit/fault information input means
701
, initial test pattern generating means
702
, the test pattern set compression system
700
, and test pattern output means
707
. The test pattern set compression system
700
includes test pattern order reversing means
703
, undefined value sensitizing means
704
, test pattern removing/undefined value setting means
705
, and test pattern merging means
706
.
The circuit/fault information input means
701
fetches the information on the configuration and faults of the target logic circuit from the outside of the generator and the, sends it to the initial test pattern generating means
702
. The information on the configuration and faults of the target logic circuit is termed the “circuit/fault information CFI” below.
The initial test pattern generating means
702
generates an initial test pattern set TPS
0
(i.e., a test pattern set to be compressed) on the basis of the circuit/fault information CFI thus received. Then, the means
702
sends the initial test pattern set TPS
0
thus generated to the test pattern order reversing means
703
. The initial test pattern set TPS
0
includes specific test patterns. Each of the patterns includes specific input signals applicable to the target logic circuit.
The test pattern order reversing means
703
reverses the order of the test patterns included in the initial test pattern set TPS
0
. Alternately, the means
703
reverses the order of the test patterns included in a fourth test pattern set TPS
4
sent from the test pattern merging means
706
explained later. Thus, due to the order-reversing operation, the initial test pattern set TPS
0
or the fourth test pattern set TPS
4
is converted to a first test pattern set TPS
1
. Then, the means
703
sends the first test pattern set TPS
1
thus generated to the undefined value sensitizing means
704
.
The undefined value sensitizing means
704
assigns the value of “0” or “1” (i.e., a low- or high-level logic signal) to the input signals of the respective test patterns in the first test pattern set TPS
1
thus received. In other words, the undefined values of “X” contained in the set TSP
1
are sensitized. Due to this sensitization of the undefined values, the set TSP
1
is converted to a second test pattern set TPS
2
. The means
704
sends the second test pattern set TPS
2
thus obtained to the test pattern removing/undefined value setting means
705
. The sensitization of undefined values eliminates the undefined logic states in the target logic circuit when simulation is carried out and therefore, there arises a possibility that any other faults are detected.
The test pattern removing/undefined value setting means
705
extracts successively the test patterns included in the second test pattern set TPS
2
thus received according to the order of the test patterns and then, simulation operations are successively carried out using the test patterns thus extracted. The means
705
identifies or specifies unnecessary test patterns from all the test patterns included in the second set TPS
2
on the basis of the simulation result. If at least one unnecessary pattern is identified by the means
705
, the at least one unnecessary test pattern thus identified is removed from the set TPS
2
. Also, the means
705
sets undefined values on the unnecessary input signals of the remaining test patterns in the set TPS
2
, respectively, thereby facilitating the test pattern merging. Thus, the second test pattern set TPS
2
is converted to a third test pattern set TPS
3
. The set TPS
3
thus formed is sent to the test pattern merging means
706
.
The test pattern merging means
706
identifies two or more mergible test patterns from the test patterns in the third test pattern set TPS
3
thus received. Then, the means
706
merges the two or more test patterns thus identified together to form a single test pattern, thereby converting the set TPS
3
to a fourth test pattern set TPS
4
. The set TPS
4
thus generated corresponds to the compressed one of the initial test pattern set TPS
0
.
Moreover, the test pattern merging means
706
makes a judgment whether or not the fourth test pattern set TPS
4
should be further compressed under a predetermined condition. If the means
706
judges further compression necessary, the means
706
returns the set TPS
4
to the test pattern order reversing means
703
and then, the means
703
,
704
,
705
, and
706
compresses the set TPS
4
again in the same way as performed for the initial test pattern set TPS
0
. If the means
706
judges further compression unnecessary, the means
706
sends the set TPS
4
to the test pattern output means
707
.
The test pattern output means
707
sends the fourth test pattern set TPS
4
thus received to the outside of the prior-art test pattern set generator of
FIG. 1
as a finally-compressed test pattern set CTPS.
The undefined value identification operation by the test pattern removing/undefined value setting means
705
and the test pattern merging operation by the test pattern merging means
706
may be performed by any known technique, for example, disclosed in the Japanese Non-Examined Patent Publication No. 8-212799 published in August 1996.
In the prior-art test pattern compression system
700
, the operations of the test pattern order reversing means
703
, the undefined value sensitizing means
704
, the test pattern removing/undefined value setting means
705
, and the test pattern merging means
706
are repeated until all the mergeable test patterns are merged. As a result, the number of the test patterns constituting the initial test pattern set TPPS
0
is decreased, in other words, the set TPS
0
is compressed.
With the prior-art test pattern compression system
700
in
FIG. 1
, the fault simulation is carried out while reversing the order of the test patterns in the initial test pattern set TPS
0
. Thus, the patterns unnecessary to fault detection (i.e., that are removable) are easily identified. Moreover, since the test pattern merging is performed while undefined values are assigned to the input signals necessary to fault detection, the unnecessary test patterns are easily merged. Thus, the test pattern compression function can be enhanced.
However the prior-art test pattern compression system
700
has the following disadvan
Foley & Lardner
NEC Electronics Corporation
Vu Viet D.
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