Test circuit and multi-chip package type semiconductor...

Details Test circuit and multi-chip package type semiconductor... Test circuit and multi-chip package type semiconductor...

2001-10-18

2004-07-13

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S048000, C257S693000

Reexamination Certificate

active

06762486

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Japanese Patent Application No. 2000-320643, filed Oct. 20, 2000, the entire disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a test circuit capable of a multi-chip package type semiconductor device (MCP semiconductor device) and an MCP semiconductor device having the test circuit.
2. Description of the Related Art
In the related art, there are several types of multi-chip packages in which more than one IC chip can be packaged. One typical multi-chip package is a stack-type multi-chip package that packages at least two IC chips in a stacked manner as shown in FIG.
7
. Another typical multi-chip package is a parallel-type multi-chip package that packages at least two IC chips in the same plane as shown in FIG.
8
.
As shown in
FIGS. 7 and 8
, Each of the MCP semiconductor devices
1
,
2
includes a first semiconductor chip (hereinafter “first chip”) C
101
and a second semiconductor chip (hereinafter “second chip”) C
102
. The first chip C
101
includes terminal pads P
101
for internal connections (hereinafter “internal pads”), and terminal pads P
111
for external connection (hereinafter “external pads”). The second chip C
102
shown in
FIG. 7
includes internal pads P
102
, and the second chip C
102
shown in
FIG. 8
includes internal pads P
102
and external pad P
112
. Each of the internal pads P
101
is connected to one of the internal pads P
102
by a bonding wire BW. Each of the external terminal pads P
111
and of the external terminal pads P
112
are connected to one of external terminal
121
by a bonding wire BW.
A process of forming the MCP semiconductor device
2
shown in
FIG. 8
includes a step for conveying the first chip C
101
and second chip C
102
, and a step for mounting the first and second chips on a printed board. A process of forming the MCP semiconductor device
1
shown in
FIG. 7
includes a step for conveying a first chip C
101
and the second chip C
102
, and a step for mounting the second chip C
102
on the first chip C
101
. In these steps, static electricity may be charged on the first and second chips C
101
, C
102
. While the static electricity may be charged on the first and second chips C
101
, C
102
, if the bonding wires BW are contacted with the internal and external pads P
101
, P
102
, P
111
, P
112
, surges may occur between the internal and external pads P
101
, P
102
, P
111
, P
112
and the bonding wires BW. As a result, a peripheral circuit, which is formed near the pads, may be damaged by the surges. When the damage is critical to the peripheral circuit, it is possible to find an MCP semiconductor device having a damaged chip by a function test. However, when the damage is not so critical to a peripheral circuit, an MCP semiconductor device having a damaged chip may not be found by the function test because the damaged circuit operates normally. Since it is difficult to find an MCP semiconductor device having a damaged chip by a function test, an MCP semiconductor device having a damaged chip is found by measuring a leakage current. According to this measurement, a judgement as to whether an MCP semiconductor device has a damaged chip, can be made.
In an MCP semiconductor device having a single chip, since a terminal pad formed on the chip is connected directly to an external terminal of a lead flame placed outside of the MCP semiconductor device, it is easy to measure a leakage current at the terminal pad by applying a voltage having an H level (ex. power supply voltage) or applying a voltage having an L level (ex. ground voltage) to the external pad. However, in an MCP semiconductor device, at least two chips are formed, and these chips are connected to each other at some of their internal pads P
101
, P
102
by the bonding wires BW, as shown in
FIGS. 7 and 8
. In other word, these internal pad P
101
, P
102
are used for connecting the first chip C
101
to the second chips C
101
, C
102
, and are not used for connecting the first and second chips C
101
, C
102
to the external terminals
121
. Therefore, it is impossible to measure leakage current on these internal pads P
101
, P
102
by applying the predetermined voltage from the outside because these internal pads P
101
, P
102
are not connected directly to the external terminal on which the predetermined voltage is applied.
Since it is impossible to measure a leakage current on these internal pads P
101
, P
102
by the method described above, the judgement as to whether an MCP semiconductor device having a damaged chip, must rely on the function test. However, as described above, the function test may not be able to find a damaged chip when the damage is not critical. As a result, the MCP semiconductor device having the damaged chip may be manufactured, and then, incorporated in a system. In the worst case, the MCP semiconductor device having the damaged chip malfunctions, and it causes the system to malfunction.
To resolve this problem, it is proposed for an MCP semiconductor device that a consuming current (IDDS) be measured under the condition that an operation of all chips is halted. However, there are some problems with this measurement.
For example, if one of two chips is a programmable memory, it takes a long time to fix the highest bit in an address to “0” or “1”. As a result, a long time is required for measuring the consuming current (IDDS) under the conduction that an operation of all chips is halted.
Further, if one of two chips is a memory, an electric current of a few mA flows in the chip when a chip select terminal is enabled. That is, when MCP semiconductor device includes a chip such as a memory chip or similar kinds, it may be impossible to set the value of the electric current to be caused to flow in the chip to zero (“0”), depending on the voltage level that is applied to each terminal. As a result, it is difficult to obtain accurate measurement results.
Moreover, if one of the two chips is an analog circuit such as an A/D converter, it is difficult to fix the internal pad P
101
, P
102
to the predetermined voltage level.
As described above, it is not easy to test the internal terminal pads and their peripheral circuits formed on each chip, according to the structure of the MCP semiconductor device
SUMMARY OF THE INVENTION
It is therefore an object of the invention to resolve the above-described problem in an MCP semiconductor device and provide an MCP semiconductor device having a test circuit for testing the MCP semiconductor device accurately and rapidly.
The object is achieved by an MCP semiconductor device including at least first and second chips encapsulated together by a sealing material. The first semiconductor chip includes a first internal circuit and a plurality of first internal terminal pads for transmitting signals to or from the first internal circuit. The second semiconductor chip includes a second internal circuit and a plurality of second internal terminal pads for transmitting signals to or from the second internal circuit. Each second internal pad is electrically connected to one the first internal terminal pads. The MCP semiconductor device further includes a test circuit, responsive to a voltage level of a test mode signal, selecting one from between the operations for prohibiting signal transmission between the first internal circuit and the first internal terminal pads and for allowing signal transmission between the first internal circuit and the first internal terminal pads, and selecting one from between the operations for prohibiting signal transmission between the second internal circuit and the second internal terminal pads and for allowing signal transmission between the second internal circuit and the second internal terminal pads.
Further, the object is achieved by an MCP semiconductor device having a test circuit for providing the test data, for storing a test result, and for connecting the external terminal pad to the internal terminal p

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