Wave transmission lines and networks – Long lines – Strip type
Reexamination Certificate
2001-04-20
2004-07-27
Lee, Benny T. (Department: 2817)
Wave transmission lines and networks
Long lines
Strip type
C333S246000
Reexamination Certificate
active
06768400
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a microstrip line, to a method for fabricating the same, to an inductor element, and to an RF semiconductor device.
As the number of users of radio communication systems including mobile phones has increased year by year, size and cost reduction has been required increasingly of mobile terminal equipment used in the radio communication systems. An RF device which is a primary component of the mobile terminal equipment has been reduced in cost by forming it into a so-called MMIC (Monolithic Microwave IC) in which an active element and a passive element are formed integrally in a substrate, instead of forming it into a multichip IC in which the active and elements are integrated separately in the substrate as has been practiced conventionally.
FIG. 15
shows a conventional RF circuit.
FIG. 16
shows a plan configuration of an RF semiconductor device in which the RF circuit shown in
FIG. 15
is implemented in a substrate. In
FIG. 16
, the same components as shown in
FIG. 15
are designated by the same reference numerals. Specifically, the RF circuit comprises a DC blocking capacitance
307
, a register
308
, a drain terminal
313
, a gate terminal
314
and a source terminal
315
.
As can be seen from
FIGS. 15 and 16
, each of passive elements including spiral inductors
302
and
303
disposed between an input terminal
311
and an amplifying FET
301
, spiral inductors
304
and
305
disposed between the drain of the FET
301
and an output terminal
312
, and a dc blocking capacitance
306
occupies an area larger than occupied by the amplifying FET
301
which is an active element.
To further reduce the RF semiconductor device in cost, it is necessary to reduce the passive elements in size and thereby increase chip yield per slice (wafer). Chip area has been reduced conventionally by using a strontium titanium oxide (STO), which is a high dielectric material, as a dielectric material composing a dc blocking capacitance or by-pass capacitance and thereby reducing the area of the capacitance (GaAs IC symposium 1998).
On the other hand, Japanese Unexamined Patent Publications Nos. HEI 8-116028 and HEI 9-148525 disclose technology for reducing the size of an inductor element by using STO as a dielectric material composing a microstrip line and thereby reducing the wavelength of a signal electromagnetic wave.
However, the conventional microstrip line has the problem of degrading the characteristics of the MMIC since, if the width of the line is reduced such that the characteristic impedance of the line or the inductance of the inductor is increased, the cross-sectional area of the line is reduced and a conductor loss is increased accordingly.
To increase the impedance of the microstrip line disclosed in Japanese Unexamined Patent Publication No. HEI 8-116028 or HEI 9-148525, in particular, it is necessary to reduce the width of the line to 0.5 &mgr;m or less since a high dielectric material is used as the dielectric material composing the microstrip line, which presents an obstacle to the practical use thereof. This is because a dielectric thin film formed by sputtering or physical or chemical vapor deposition such as CVD is difficult to increase in thickness. In order to increase the impedance of a microstrip line, in general, it is necessary to reduce the width of the linear conductor portion, which increases a conductor loss in the linear conductor portion.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to prevent an increase in conductor loss even if the width of a microstrip line is reduced such that the impedance of the microstrip line or the inductance of an inductor element is increased and thereby solve the foregoing problem encountered by the prior art.
To attain the object, a microstrip line according to the present invention comprises: a ground conductor layer; a dielectric layer formed on the ground conductor layer; and a linear conductor layer formed on the dielectric layer to have a linear configuration, the linear conductor layer having a wider portion in an upper part of a cross section thereof taken in a direction perpendicular to a direction in which the linear conductor layer extends and a narrower portion in a lower part of the cross section, the narrower portion being smaller in width than the wider portion.
In the microstrip line of the present invention, an increase in conductor loss is prevented since the impedance and inductance can be increased in the part thereof closer to the dielectric layer and, in addition, the upper part thereof at a distance from the dielectric layer is larger in width than the narrower portion. This allows a reduction in the size of an RC semiconductor device without degrading the operation characteristics thereof.
Preferably, the microstrip line of the present invention further comprises a substrate for holding the ground conductor layer, the substrate being located under the ground conductor layer and composed of a dielectric material, wherein the dielectric layer has a dielectric constant higher than a dielectric constant of the substrate. In the arrangement, the wavelength of an RF signal propagating through the linear conductor is reduced so that an RF circuit is surely reduced in size.
In the microstrip line of the present invention, the dielectric layer preferably contains a titanium oxide.
In this case, the titanium oxide is preferably a strontium titanate.
A method for fabricating a microstrip line according to the present invention comprises the steps of: forming a ground conductor layer on a substrate composed of a dielectric material; forming a dielectric layer on the ground conductor layer; forming a mask pattern having a linear opening on the dielectric layer; depositing a layer forming a linear conductor layer on the mask pattern including the opening; and patterning the linear-conductor-layer forming layer such that the linear-conductor-layer forming layer on the mask pattern has a width larger than a width of the opening.
The method for fabricating a microstrip line of the present invention forms the linear-conductor-layer forming layer such that the width of the linear-conductor-layer forming layer is larger than the width of the opening, thereby forming the linear conductor layer having the wider portion in the upper part of the cross section and the narrower portion narrower than the wider portion in the lower part of the cross section. This ensures the formation of the wider portion and the narrower portion of the linear conductor layer of the microstrip line according to the present invention.
An inductor element according to the present invention comprises a microstrip line composed of a ground conductor layer, a dielectric layer formed on the ground conductor layer, and a linear conductor layer formed on the dielectric layer to have a linear configuration, the linear conductor layer being formed in a spiral configuration in a plane parallel to the dielectric layer and having a wider portion in an upper part of a cross section thereof taken in a direction perpendicular to a direction in which the linear conductor layer extends and a narrower portion in a lower part of the cross section, the narrower portion being smaller in width than the wider portion.
An RF semiconductor device according to the present invention comprises: an active element formed in a substrate; and a microstrip line formed on the substrate to propagate input/output signals to and from the active element, the microstrip line being composed of a ground conductor layer formed on the substrate, a dielectric layer formed on the ground conductor layer, and a linear conductor layer formed on the dielectric layer to have a linear configuration, the linear conductor layer having a wider portion in an upper part of a cross section thereof taken in a direction perpendicular to a direction in which the linear conductor layer extends and a narrower portion in a lower part of the cross section, the narrower portion being smaller in width than the wider p
Lee Benny T.
Nixon & Peabody LLP
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