Television – Format conversion
Reexamination Certificate
1999-08-02
2004-01-06
Miller, John (Department: 2614)
Television
Format conversion
C348S446000, C348S448000, C348S558000
Reexamination Certificate
active
06674478
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to an image processing apparatus and method as well as a providing medium, and more particularly to an image processing apparatus and method as well as a providing medium by which a picture size and a vertical frequency of a video signal can be converted while suppressing line flickering without deterioration of a vertical resolution.
Television broadcasting in Japan is-based on the NTSC color TV system, and television receivers in Japan are usually designed so as to receive and display an interlaced video signal (525i) having 525 scanning lines. Meanwhile, also television receivers which can display an interlaced video signal of 625i of the PAL system, an interlaced video signal of 1080i used for high definition television broadcasting and a non-interlaced video signal of 525p for displaying line sequentially 525 scanning lines begin to be put on the market. If any of video signals of 525i, 625i, 525p and 1080i is inputted to a television receiver of the type mentioned, the television receiver converts the inputted video signal into and displays an image of a predetermined size of a predetermined unified frequency. The unified frequency may be, for example, 525p. In this instance, the horizontal scanning frequency fh is 31 kHz, and the field (frame) frequency fv is 60 Hz.
FIG. 9
shows an example of a configuration of a conventional television receiver of the type described above. Referring to
FIG. 9
, an A/D converter
1
converts analog video signals Yi
1
, Ui
1
and Vi
1
of a first frequency inputted to the television receiver into digital signals and outputs the digital signals to a low-pass filter (LPF)
2
. The LPF
2
extracts only predetermined low frequency components from horizontal and vertical frequency components of the signals inputted thereto and outputs the extracted low frequency components to an interpolation circuit
3
. The interpolation circuit
3
reduces the image data inputted thereto from the LPF
2
by interpolation calculation and supplies the reduced video signals to a frame memory
4
. Writing and reading operations of the frame memory
4
are controlled by a write memory controller
5
and a read memory controller
6
, respectively. Another interpolation circuit
7
converts data read out from the frame memory
4
into video data of a greater screen and outputs the resulting video data to a mixing (Mix) circuit
15
.
Processes similar to those performed by the components from the A/D converter
1
to the interpolation circuit
7
are performed also for other video signals Yi
2
, Ui
2
and Vi
2
by a different set of components from an A/D converter
8
to another interpolation circuit
14
which are similar to the components from the A/D converter
1
to the interpolation circuit
7
, respectively.
The mixing circuit
15
selects outputs of the interpolation circuit
7
or outputs of the interpolation circuit
14
and outputs the selected outputs to a D/A converter
16
. The D/A converter
16
converts the video signals inputted thereto in the form of digital signals into analog signals and outputs the analog signals to a display unit such as a cathode ray tube (CRT) not shown.
In operation, the A/D converter
1
converts analog signals inputted thereto into digital signals and outputs the digital signals to the LPF
2
. The LPF
2
extracts predetermined low frequency components of the inputted video signals and outputs the low frequency components to the interpolation circuit
3
. The interpolation circuit
3
performs a reduction process by linear interpolation if it is required to reduce the inputted video signals, and supplies the reduced video signals to the frame memory
4
so that they may be stored into the frame memory
4
. The write memory controller
5
controls the writing process of the reduced video signals into the frame memory
4
.
The video signals stored in the frame memory
4
are read out under the control of the read memory controller
6
and supplied to the interpolation circuit
7
. The interpolation circuit
7
processes the video signals read out from the frame memory
4
to expand the size of a screen by interpolation processing when necessary, and outputs the video signals of the expanded screen size to the mixing circuit
15
.
Similar processing is performed also by the components from the A/D converter
8
to the interpolation circuit
14
, and resulting video signals are supplied to the mixing circuit
15
.
The mixing circuit
15
selects the video signals inputted from the interpolation circuit
7
or the video signals inputted from the interpolation circuit
14
and outputs the selected video signals to the D/A converter
16
. The D/A converter
16
converts the video signals in the form of digital signals into analog signals and outputs the analog signals to the CRT or the like display unit not shown.
The television receiver thus converts, for example, video signals of 1080i, video signals of 525i or video signals of 625i into video signals of 525p in regard to the screen size and the number of scanning lines as seen in
FIG. 10
so that the video signal of 525p may be displayed.
FIG. 11
shows an example of a more detailed configuration of a portion of the television receiver shown in
FIG. 9
which includes the frame memory
4
, write memory controller
5
and read memory controller
6
described above. A digital video signal outputted from the interpolation circuit
3
is inputted to a field memory
34
and a field memory
35
which correspond to the frame memory
4
. Also a write side memory control signal (for example, an enable signal) supplied from a circuit not shown is supplied to the field memory
34
and the field memory
35
. A switch
33
is switchable to a contact “a” side or a contact “b” side in response to the write side field switching signal supplied thereto from a circuit not shown.
Also a read side memory control signal (enable signal) is supplied to the field memory
34
and the field memory
35
through another switch
37
. The switch
37
is switchable to a contact “a” side or a contact “b” side in response to the read side field switching signal outputted from a D-type flip-flop
32
. Also a further switch
36
is switchable to a contact “a” side or a contact “b” side in response to the read side field switching signal and outputs a vide signal read out from the field memory
34
or the field memory
35
to the interpolation circuit
7
.
The D-type flip-flop
32
latches the write side field switching signal in response to a read side readout start pulse detected by and outputted from a start position detection circuit
31
and outputs the latched write side field switching signal as a read side field switching signal to the switch
36
and the switch
37
.
Operation of the circuit shown in
FIG. 11
is described with additional reference to time charts of
FIGS. 12A through 12E
.
The switch
33
is switched to the contact “a” side in response to a level change of the write side field switching signal (
FIG. 12B
) to the high level, but switched to the contact “b” side in response to a level change of the write side field switching signal to the low level. A write side line address count signal (
FIG. 12A
) is supplied to the field memory
34
when the write side field switching signal (
FIG. 12B
) has the high level, but is supplied to the field memory
35
when the write side field switching signal has the low level. As a result, a digital video signal supplied from the interpolation circuit
3
is written into the field memory
34
when the write side field switching signal (
FIG. 12B
) has the high level, but is written into the field memory
35
when the write side field switching signal has the low level.
On the other hand, the write side field switching signal (
FIG. 12B
) is latched by the D-type flip-flop
32
in synchronism with a read side readout start pulse (
FIG. 12D
) outputted from the start position detection circuit
31
and is supplied as a read side field switching signal (
FIG. 12E
) to the switch
36
and the swit
Miyazaki Shinichiro
Ohno Takeshi
Shirahama Akira
Frommer William S.
Frommer & Lawrence & Haug LLP
Miller John
Sony Corporation
Tran Trang U.
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