Flash memory device having four-bit cells

Details Flash memory device having four-bit cells Flash memory device having four-bit cells

2002-12-10

2004-05-11

Lam, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185260, C365S185330

Reexamination Certificate

active

06735124

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to the field of non-volatile memory devices and, more particularly, to a semiconductor/oxide-nitride-oxide on semiconductor (SONOS) type electrically erasable programmable read only memory (EEPROM) device having at least four charge storing cells and a method of programming the same.
BACKGROUND
A pervasive trend in modern integrated circuit manufacture is to increase the number of bits stored per unit area on an integrated circuit memory core that contains memory devices (sometimes referred to as memory cells), such as flash electrically erasable programmable read only memory (EEPROM) devices. For instance, a conventional semiconductor/oxide-nitride-oxide on semiconductor (SONOS) type memory device is capable of storing two bits of data in “double-bit” format. That is, one bit can be stored using a memory cell on a first side of the memory device and a second bit can be stored using a memory cell on a second side of the memory device.
For example,
FIG. 1
illustrates a conventional, non-volatile, SONOS-type memory device
10
, which includes a semiconductor substrate
12
having a source
14
and a drain
16
formed therein. A body
18
having a channel region
20
is formed between the source
14
and the drain
16
. An oxide-nitride-oxide (ONO) dielectric stack is formed above the body
18
. A polysilicon gate electrode
32
is formed over the ONO stack. The ONO stack includes a first or bottom dielectric layer
26
(often referred to as a bottom tunnel oxide), a charge storing layer
28
, and a second or top dielectric layer
30
. Within the charge storing layer
28
, the conventional memory device
10
includes a first charge storing cell or normal bit
36
and a second charge storing cell or complementary bit
38
.
The memory device
10
is operatively arranged to be programmed, read and erased by the application of appropriate voltage potentials. Typically, the gate electrode
32
can be coupled to a wordline (WL), the source
14
can be coupled to a first bitline (BL
1
), and the drain can be coupled to a second bitline (BL
2
) for applying the various voltage potentials to the corresponding components of the memory device.
Programming of such a SONOS device can be accomplished, for example, by hot electron injection. Hot electron injection involves applying appropriate voltage potentials to each of the gate electrode
32
, the source
14
, and the drain
16
of the SONOS memory device
10
for a specified duration until the charge storing layer
28
accumulates charge. Such a process, with respect to a NOR architecture SONOS device, is disclosed in co-owned U.S. Pat. No. 6,215,702, which is incorporated herein by reference in its entirety.
During hot electron injection, one or both of the charge storing cells
36
,
38
within the charge storing layer
28
are programmed by applying appropriate potentials to the source
14
, drain
16
, and/or gate electrode
32
. The applied potentials generate a vertical electric field through the top and bottom dielectric layers
30
,
26
and the charge storing layer
28
as well as a lateral electric field along the length of the channel
20
from the source to the drain within the body
18
. The lateral electric field causes electrons to be drawn off of the source
14
and begin accelerating toward the drain
16
. As electrons move along the length of the channel
20
, the electrons gain energy and, upon attaining enough energy, jump over the potential barrier of the bottom dielectric layer
26
and into the charge storing layer
28
(within the respective charge storing cells
36
,
38
) where the electrons become trapped.
While conventional NOR architecture SONOS devices are capable of storing two bits per memory device, there is an ever increasing demand to store even more data per unit area of a memory core.
SUMMARY OF THE INVENTION
According to one aspect of the invention, the invention is directed to a non-volatile memory device. The memory device includes a source and a drain, which have a channel region therebetween. A bottom dielectric layer is formed over the channel region and a charge storing layer is formed over the bottom dielectric layer. The charge storing layer includes at least four charge storing cells. Sidewalls are disposed on opposite sides of the charge storing layer. A top dielectric layer is formed over the charge storing layer and a gate electrode is formed over the top dielectric layer. A first complementary conductive region is disposed adjacent the first sidewall of the charge storing layer and a second complementary conductive region is disposed adjacent a second sidewall of the charge storing layer.
According to another aspect of the invention, the invention is directed to a method of programming a memory device. The memory device can include a charge storing layer having at least four charge storing cells. The charge storing layer is disposed between a top dielectric layer and a bottom dielectric layer. A gate electrode is disposed over the top dielectric layer. The bottom dielectric layer is disposed over a substrate having a source, which is coupled to a first bitline, and a drain, which is coupled to a second bitline. First and second complementary bitlines, which are disposed on opposite sides of the charge storing layer, extend along a direction perpendicular to the first and second bitlines. The method includes programming a selected charge storing cell by applying a voltage potential to each of the gate electrode and the bitline and complementary bitline adjacent to the selected charge cell.
According to another aspect of the invention, the invention is directed to a method of reading a memory device. The memory device can include a charge storing layer having at least four charge storing cells. The charge storing layer is disposed between a top dielectric layer and a bottom dielectric layer. A gate electrode is disposed over the top dielectric layer. The bottom dielectric layer is disposed over a substrate having a source, which is coupled to a first bitline, and a drain, which is coupled to a second bitline. First and second complementary bitlines, which are disposed on opposite sides of the charge storing layer, extend along a direction perpendicular to the first and second bitlines. The method includes reading a selected charge storing cell by applying a voltage potential to each of the gate electrode and the bitline and complementary bitline opposite the selected charge storing cell and grounding the bitline adjacent to the selected charge storing cell.
According to another aspect of the invention, the invention is directed to a method of simultaneously erasing at least four charge storing cells within a memory device. The memory device can include a charge storing layer, which contains at least four charge storing cells, disposed between a top dielectric layer and a bottom dielectric layer. A gate electrode, which is formed from a wordline, is disposed over the top dielectric layer. The bottom dielectric layer is disposed over a substrate including a source, which is formed from a first bitline, and a drain, which is formed from a second bitline. First and second complementary bitlines, which are disposed on opposite sides of the charge storing layer, extend along a direction perpendicular to the first and second bitlines. The method includes applying a negative gate erase voltage of about −6 Volts or less to the wordline, applying a voltage of about +3 Volts or less to the first and second complementary bitlines, and coupling the first and second bitlines to a potential of about +6 Volts or less.


REFERENCES:
patent: 5903494 (1999-05-01), Papadas et al.

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