Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2002-07-10
2004-09-14
Nguyen, Long (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S537000, C326S068000
Reexamination Certificate
active
06791391
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a level shifting circuit (level conversion circuit) that operates with a plurality of power source voltages in a semiconductor integrated circuit device.
2. Related Background Art
The following will describe a conventional level shifting circuit referring to the drawings.
FIG. 4
is a circuit diagram illustrating a conventional level shifting circuit.
A level shifting circuit
100
is a circuit that is built in a LSI and shifts the level of a low voltage signal supplied from an external input terminal IN to a high voltage signal, to output the same through an external output terminal OUT. Here, the low voltage signal is a digital signal whose high level is a first power source voltage Vddl and whose low level is 0V. The high voltage signal obtained by level shifting is a digital signal whose high level is a second power source voltage Vddh and whose low level is 0V. Among power source voltages in the LSI, appropriate ones are used as the first and second power source voltages Vddl and Vddh, respectively.
In
FIG. 4
,
21
denotes a first inverter for a low-voltage operation, and
22
denotes a second inverter for a low-voltage operation.
23
denotes a first P-channel transistor for a high voltage operation, and
24
denotes a second P-channel transistor for a high voltage operation. Sources thereof are connected to substrates thereof.
25
denotes a first N-channel transistor for a high voltage operation, and
26
denotes a second N-channel transistor for a high voltage operation. Substrates thereof are connected to GND.
The following will describe an operation of the conventional level shifting circuit
100
, while referring to
FIG. 4. A
case where a low voltage signal transmitted from the external input terminal IN is at a L level (0V) is described first. A low voltage signal is inverted by the first inverter
21
, and a node n
5
is pulled up to a H level (Vddl), which causes a voltage at the H level (Vddl) to be supplied to a source of the first N channel transistor
25
. Here, since a voltage at the H level (Vddl) is applied to a gate of the first N-channel transistor
25
, the first N-channel transistor
25
becomes non-conducting.
On the other hand, a signal branched at the node n
5
is inverted by the second inverter
22
, and a node n
6
is pulled down to a L level (0V). Therefore, a voltage at the L level (0V) is applied to a source of the second N-channel transistor
26
. Here, since a voltage at the H level (Vddl) is applied to a gate of the second N-channel transistor
26
, the second N-channel transistor
26
becomes conducting. Therefore, a node n
8
is pulled down to the L level (0V).
Furthermore, a H level (Vddh) of the high voltage signal is applied to a source of the first P-channel transistor
23
, and a gate of the first P-channel transistor
23
(node n
8
) is at the L level (0V), thereby causing the first P-channel transistor
23
to become conducting. Therefore, a node n
7
is pulled up to the H level (Vddh).
Furthermore, the H level (Vddh) of the high voltage signal is applied to a source of the second P-channel transistor
24
, and a gate of the second P-channel transistor
24
(node n
7
) is at the H level (Vddh), thereby causing the second P-channel transistor
24
to become non-conducting. As a result, an external output terminal OUT (node n
8
) is stabilized at the L level (0V).
The following will describe a case where the low voltage signal supplied through the external input terminal IN is at the H level (Vddl). The low voltage signal is inverted by the first inverter
21
, and the node n
5
is pulled down to the L level (0V), whereby a voltage at the L level (0V) is applied to the source of the first N-channel transistor
25
. Here, since a voltage at the H level (Vddl) is applied to a gate of the first N-channel transistor
25
, the first N-channel transistor
25
becomes conducting. This causes the node n
7
to be pulled down to the L level (0V).
Furthermore, the H level (Vddh) of the high voltage signal is applied to the source of the second P-channel transistor
24
and the gate of the second P-channel transistor
24
(node n
7
) is at the L level (0V), thereby causing the second P-channel transistor
24
to become conducting. Therefore, the node n
8
is pulled up to the H level (Vddh).
On the other hand, the signal branched at the node n
5
is inverted by the second inverter
22
, and the node n
6
is pulled up to the H level (Vddl), thereby causing a voltage at the H level (Vddl) to be applied to the source of the second N transistor
26
. Here, since a voltage at the H level (Vddl) is applied to the gate of the second N-channel transistor
26
, the second N-channel transistor
26
becomes non-conducting.
Furthermore, a voltage at the H level (Vddh) is applied to the source of the first P-channel transistor
23
, and the gate of the first P-channel transistor
23
(node n
8
) is at the H level (Vddh), thereby causing the first P-channel transistor
23
to become conducting. This causes the external output terminal OUT (node n
8
) to be stabilized at the H level (Vddh).
Thus, the conventional level shifting circuit
100
is capable of carrying out the level conversion with respect to a low voltage signal supplied thereto and outputting a high voltage signal.
In the aforementioned level shifting circuit
100
, it is necessary to lower a power source voltage inside a LSI in the case where a withstand voltage of a transistor lowers as the power consumption of electronic devices is lowered as demanded and the micromachining is promoted in the manufacturing process. However, if the first power source voltage Vddl becomes lower than 1.5V, a propagation delay time from the input to the output to/from the level shifting circuit
100
increases significantly. This is because the time required for charging the gates of the first and second N-channel transistors
25
and
26
increases if the power source voltage Vddl is lowered.
Furthermore, in the case where the power source voltage Vddl is lowered to approximately 1.0V, the first and second N-channel transistors
25
and
26
cannot operate. This is because the power source voltage Vddl supplied to the gate of the first or second N-channel transistor
25
or
26
approaches the threshold voltage for the first and second N-channel transistors
25
and
26
. Thus, the conventional level shifting circuit
100
has a drawback in that it does not function in the case where the power source voltage Vddl is lowered excessively.
SUMMARY OF THE INVENTION
Therefore, with the foregoing in mind, it is an object of the present invention to provide a level shifting circuit that outputs a signal that has been subjected to stable level conversion, even when a voltage level of a low voltage signal lowers.
A level shifting circuit of the present invention is a CMOS level shifting circuit including a N-channel transistor that has a source to which a digital signal is supplied. In the CMOS level shifting circuit, a bias voltage is supplied to a gate of the N-channel transistor, and the bias voltage is set to be higher than a high level voltage of the digital signal and lower than a value obtained by adding a threshold voltage of the N-channel transistor to the high level voltage of the digital signal. This allows the N-channel transistor to operate even when the digital signal is at a low voltage level, and hence, makes it possible to provide a level shifting circuit capable of carrying out level conversion of an input signal and outputting a result.
The bias voltage preferably is one of power source voltages. This allows the N-channel transistor to operate by using a power source voltage that is already available, without applying an additional voltage.
A level shifting circuit of the present invention is a CMOS level shifting circuit including a first N-channel transistor, a second N-channel transistor, a first P-channel transistor, and a second P-channel transistor. In the CMOS level shifting circuit, a drain of t
Gion Masahiro
Ikoma Heiji
Nishimura Hidetoshi
Nojiri Naoki
Matsushita Electric - Industrial Co., Ltd.
Merchant & Gould P.C.
Nguyen Long
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