Pulse or digital communications – Spread spectrum – Direct sequence
Reexamination Certificate
2001-12-28
2004-09-14
Ghebretinsae, Temesghen (Department: 2631)
Pulse or digital communications
Spread spectrum
Direct sequence
C375S130000, C370S335000, C370S342000
Reexamination Certificate
active
06792032
ABSTRACT:
BACKGROUND
The present invention relates to wireless digital communication systems. More particularly, the present invention relates to a method and apparatus for convolution of spreading code, scrambling code and channel response within a wireless TD-CDMA communication receiver to calculate system transmission matrix coefficients.
During communications in a TD-CDMA system such as specified by the Third Generation Partnership Project (3GPP), each signal burst between a base station and a user equipment (UE) is transmitted and received along a frame structure that is broken into time slots.
FIG. 1
shows the structure of a communication burst time slot comprising a predetermined midamble, specifically assigned by a base station to a UE for channel estimation purposes, located between two data symbol bursts. The midamble information is characterized by a number of chips, where T
C
represents the chip period and L
m
is the midamble length. The midamble chips are transformed by a filter process in the receiver into a channel response consisting of real and imaginary components. Because a TD-CDMA system allows several UEs to be assigned to the same time slot, each has a unique spreading code and spreading factor tagged to it to distinguish one UE's midamble channel representation from another. Scrambling codes are attached to a signal to distinguish one base station from another, thereby preventing inter-base station interference, which potentially occurs when a UE is in the range of two nearby base stations.
As a wireless transmission travels through the air between a transmitter and a receiver, signal reflections and external noise effects create a received signal that is different from its original state. Therefore, within the communication system, it is useful to develop a representation of the known system transmission characteristics unique to the particular base station and UE. In 3GPP systems, a system transmission matrix A of coefficient values, and/or its complex conjugate transpose A
H
, is used for this purpose. Applying the received signal to the system transmission matrix coefficients is a way to extract the original signal data from the externally altered signal that was received.
SUMMARY
The present invention provides an apparatus and method for data processing particularly useful in combining convolutions of the spreading code, scrambling code and channel response in order to construct a system transmission coefficient matrix, while maintaining the same circuit size and execution time relative to performing any one convolution separately.
The invention includes an apparatus and method for inter alia processing a series of dual element data values V
1
to V
x
such as complex number representations where data value V
m
, for each integer m from 1 to x, corresponds to a first element A
m
and a second element B
m
, with a N bit binary value, where N is a positive even integer, to produce a series of data values V′
1
to V′
y
where data value V′
p
, for each integer p from 1 to y, corresponds to a first element A′
p
and a second element B′
p
. Preferably, the series of data values V
1
to V
x
represent channel response values of a communication signal that has a spreading factor of 2
M
where M is an integer and 2
M
≦N. In such case, the N bit binary value represents a channel code value associated with the communication signal and the series of data values V′
1
to V′
y
represents a row of values of a system transmission matrix. N is preferably a power of 2.
A first element shift register R
1
and a second element shift register R
2
are provided. Each register R
1
,R
2
has a series of N locations Ci for each integer i from 1 to N. Each register R
1
,R
2
is associated with a first component adder circuit A
1,1
, A
1,2
, respectively, and a second component adder circuit A
2,1
, A
2,2
, respectively.
Each adder circuit has a series of N/2 selectively controllable inputs I
k
, for each integer k from 1 to N/2. Each adder circuit input is coupled with a different register location to receive data therefrom. Each adder circuit input is controllable via a control bit associated with its respective register location, where the control bits collectively correspond to the N bit binary value. Each control bit B
i
associated with a location Ci of register R
R
is the same as the control bit B
i
associated with corresponding location Ci of register R
I
for each integer i from 1 to N, such that the input receives data from the location to which it coupled as a value or an inverse value of the received data, dependent upon the value of the control bit. Each adder circuit has an output for outputting the sum of the values received by its respective controllable inputs.
Preferably, the first component adder circuit A
1,1
is coupled with the register R
1
such that input I
k
receives data from register location C
2
k−
1, for each integer k from 1 to N/2. The second component adder circuit A
2,1
is coupled with the register R
1
such that input I
k
receives data from register location C
2
k
, for each integer k from 1 to N/2. The first component adder circuit A
1,2
is coupled with the register R
2
such that input I
k
receives data from register location C
2
k
, for each integer k from 1 to N/2. The second component adder circuit A
2,2
is coupled with the register R
2
such that input I
k
receives data from register location C
2
k−
1, for each integer k from 1 to N/2.
A first component combiner circuit is coupled to the outputs of the first component adder circuits A
1,1
, A
1,2
for outputting a first element value A′
p
of a processed value V′
p
. A second component combiner circuit is coupled to the outputs of the second component adder circuits A
2,1
, A
2,2
for outputting a second element value B′
p
of a processed value V′
p
.
The registers R
R
, R
I
are operable to shift the data of their respective locations and receive new data to thereafter generate a next processed value V′
p+1
. Preferably, the registers R
1
, R
2
are operable to shift the data of respective locations Ci−1 to locations Ci for each integer i from 2 to N and receive new data in location C
1
to thereafter generate the next processed value.
Preferably, a control circuit is provided that operatively controls the registers and adder circuits based on the spreading factor of a communication corresponding to the data value series to be processed. The control circuit is operative to sequentially input the series of data values V
1
to V
x
followed by a series of N−1 zero values to the registers N/2
M
times to produce N/2
M
series of data values V′
1
to V′
y
, where y=x+N−1, each representing a row of values of the system transmission matrix. The control circuit is operative to selectively enable and disable the inputs of the adder circuits when 2
M
<N such that each time the series of data values V
1
to V
x
is input to the registers, a different set of 2
M
inputs are enabled from each register with all other adder inputs being disabled.
Preferably, registers R
1
and R
2
are 16-location type (N=16) with F bits per location, are used for moving channel responses through the convolution. In place of multipliers, an optimized minimum number of adders connected in a pyramid configuration are used to perform the necessary multiplication of the codes, for simplicity of construction. By including the channel code transformation from binary representation to complex representation as part of the overall method, unnecessary adders are eliminated from the apparatus.
Other objects and advantages will be apparent to those skilled in the art from the following descriptions.
REFERENCES:
patent: 2004/0001465 (2004-01-01), Timmerman et al.
Becker Peter Edward
Buchert Ryan Samuel
Fazili Muhammad Usman
Timmerman Chayil
Ghebretinsae Temesghen
InterDigital Technology Corporation
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