Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2002-03-13
2004-09-14
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S210000, C377S069000, C365S081000
Reexamination Certificate
active
06791526
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a drive voltage designed to sequentially energize a plurality of output lines, and more particularly to a drive voltage designed to sequentially energize the gate lines of a TFT liquid-crystal display.
BACKGROUND OF THE INVENTION
FIG. 14
is a schematic block diagram depicting a common TFT (Thin Film Transistor) liquid-crystal display.
In
FIG. 14
,
1
is a TFT,
2
a liquid crystal,
3
a gate drive circuit,
4
a data drive circuit, and
5
a timing control circuit.
Pixel cells composed of TFTs
1
and liquid crystals
2
are arranged in a matrix at intersections between the gate lines of the gate drive circuits
3
and the data lines of the data drive circuits
4
, as shown in FIG.
14
.
As a switch for controlling the voltage applied to the liquid crystal of each pixel cell, each TFT
1
is switched on or off depending on the gate line drive signal OUTk (1≦k≦n) from the corresponding gate drive circuit
3
. In an off-position, the liquid crystals and the data lines of the data drive circuits
4
are connected, and the voltage from the data lines is applied to the liquid crystals.
Each liquid crystal
2
is connected between a common terminal COM and the drain of a TFT
1
and is designed to vary light transmission in accordance with the voltage applied from the data line of the corresponding data drive circuit
4
via the TFT
1
.
Each gate drive circuit
3
operates such that drive signals for sequentially energizing the gate lines connected to the TFT gates of each row of the pixel matrix are generated in accordance with the control signals from the timing control circuits
5
. The TFTs of the pixel cells lying on the same line are switched on at the same time by the drive signals from the gate drive circuits
3
.
The data drive circuits
4
are configured such that video signals Sc provided in synchronism with a horizontal sync signal are sequentially retained for each of the pixels of the pixel matrix in accordance with the control signals from the timing control circuits
5
, and drive signals for energizing the data lines are generated in accordance with the video signals Sc of the pixels thus retained.
The timing control circuits
5
generate control signals whereby the video signals Sc of individual pixels are sequentially retained by the data drive circuits
4
on the basis of the horizontal or vertical sync signals of the video signals Sc. In addition, each gate drive circuit
3
generates a control signal for energizing the gate line with the timing (horizontal retrace periodicity) at which a video signal Sc corresponding to a single horizontal line is retained by the data drive circuit
4
.
In a TFT liquid-crystal display thus configured, the video signals Sc presented to data drive circuits
4
are retained by each pixel of a horizontal line with a timing that corresponds to the control signals from the timing control circuits
5
. The data lines corresponding to the pixels of the horizontal line are energized in accordance with the magnitude of the video signals Sc thus retained. Specific gate lines are energized with the timing that corresponds to the control signals from the timing control circuits
5
, the TFTs of the pixel cells connected to these gate lines are switched on at the same time, and the drive voltage of each data line is applied to the liquid crystal. The applied voltage of each pixel cell is sequentially refreshed by repeating these operations for each horizontal line.
A conventional example of the gate drive circuit
3
shown in
FIG. 14
will now be described.
FIG. 15
is a schematic block diagram illustrating an example of a conventional TFT gate drive circuit with three voltage levels. The circuit comprises 265 output channels designed to energize gate lines.
In
FIG. 15
,
6
is an input level shifting circuit,
8
a 265-bit bidirectional shift register circuit,
9
a decoding circuit,
10
an output level shifting circuit, and
11
an output buffer circuit.
The input level shifting circuit
6
allows the logic level of an input/output signal (between the power voltage VDD and the reference voltage VSS) to be shifted to the internal logic level of a gate drive circuit (between the power voltage VDL and the reference voltage VEE). Specifically, the levels of clock signals CPV, shift data STV
1
and STV
2
, shift direction switching signals L/R, and other input/output signals are converted to the internal logic level of the gate drive circuit, and the input/output signals thus converted are presented to the bidirectional shift register
8
or decoding circuit
9
.
The bidirectional shift register
8
operates such that the shift data STV
1
(or shift data STV
2
) from the input level shifting circuit are sequentially shifted in synchronism with the clock signal CPV in the shifting direction that corresponds to the shift direction switching signals L/R. In addition, the shift data STV
2
(or shift data STV
1
) shifted following the end bits of the shift register are sequentially presented to the input level shifting circuit
6
.
The decoding circuit
9
generates three-bit data obtained by combining each bit of the bidirectional shift register
8
with the preceding and following bits, produces two-bit data for decoding shift direction switching signals L/R and selecting one of three voltage levels, and outputs the results to the output level shifting circuit
10
associated with the corresponding bits.
The output level shifting circuit
10
is a circuit whereby the signal level of the two-bit data obtained from the decoding circuit
9
is shifted to the high-voltage input signal level of the output buffer circuit
11
. For example, the signal output from the decoding circuit
9
, whose signal level is about 3 V in relation to the reference voltage VEE, is shifted by the output level shifting circuit
10
to a signal level of about 40 V and is presented to the output buffer circuit
11
.
The output buffer circuit
11
operates such that one of three specific voltage levels is selected in accordance with the two-bit data obtained from the decoding circuit
9
via the output level shifting circuit
10
, and the gate line is energized by a signal having the voltage level thus selected.
The operation of the TFT gate drive circuit thus configured (
FIG. 15
) will now be described with reference to
FIGS. 16-18
.
FIG. 16
is a diagram depicting the voltage level of an input/output signal and the voltage level of a gate line drive signal. Specific examples of such voltage levels are shown on the right side of the drawing.
For example, the internal reference voltage VEE may be set low (about 3-20 V in relation to the external reference voltage VSS) and the internal logic power voltage VDL may be set high (about 2.3-3.6 V in relation to the reference voltage VEE), as shown in FIG.
16
. In addition, the power voltage VCOM and power voltage VL from the output buffer circuit
11
may be set such that, for example, the power voltage VCOM is about 10-30 V greater than the reference voltage VSS, and the power voltage VL is about 0-10.5 V greater than the reference voltage VEE.
FIG. 17
is a diagram depicting the waveform of the gate line drive signal with three voltage levels provided by the TFT gate drive circuit shown in FIG.
15
.
The gate line drive signal from each output channel in a normal state is kept at the voltage level of the power voltage VL, as shown in FIG.
17
. The voltage level of the gate line drive signal rises from the power voltage VL to the power voltage VCOM during the energizing of the gate line, and this voltage level is maintained for the duration of a single clock signal CPV, which is equal to the horizontal scanning period of a pixel signal. In the next horizontal scanning period, the voltage level decreases from the power voltage VCOM to the reference voltage VEE, and this voltage level is maintained for another horizontal scanning period. Such gate line drive signals are sequentially outputted from the output channels in synchronism with the clock signal CPV.
Kubota Yasushi
Satoh Tatsumi
Brady III W. James
Kempler Wiliam B.
Piziali Jeff
Shalwala Bipin
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