TFI probe I/O wrap test method

Details TFI probe I/O wrap test method TFI probe I/O wrap test method

2002-01-04

2004-05-04

Karlsen, Ernest (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S537000, C324S754090

Reexamination Certificate

active

06731128

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a structure and method for testing external connections on semiconductor devices. The present invention also relates to a method for forming a structure for testing external connections on semiconductor devices.
BACKGROUND OF THE INVENTION
Semiconductor device manufacturing involves many process and testing steps. This testing often includes testing the functioning of elements of the semiconductor devices as well as the integrity of the structure making up the connections and elements. Typically, the testing is carried out by contacting connections on the semiconductor devices with one or more testing apparatuses. A testing apparatus is usually connected to the connections.
SUMMARY OF THE INVENTION
The present invention provides a structure for testing external connections to semiconductor devices. The structure includes an external electrical path between selected pairs of external connections on the semiconductor devices.
Additionally, the present invention provides a method for testing external connections to a semiconductor device. The method includes providing an external electrical path between selected pairs of external connections on the semiconductor devices. Testing is then carried out by sending at least one signal through the external electrical path.
Furthermore, the present invention provides a method for forming a structure for testing external connections to semiconductor devices. The method includes providing a thin film of electrically insulating material. A plurality of passages are provided through the thin film of electrically insulating material. The passages are arranged in a pattern corresponding to a pattern of external connections on the semiconductor device. Electrically conducting material is provided in the plurality of passages. Electrical connections are provided between the electrically conducting material in selected pairs of the plurality of passages.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described only the preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.


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W.H. McAnney, “Improving the Fault Coverage of Boundary Scan”, Research Disclosure, Mar. 1991, No. 323, England.
“Contactless On-Chip AC I/O Wrap Test”, Research Disclosure 41, Sep. 1998, Kenneth Mason Publications Ltd., England.

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