Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2003-03-25
2004-07-20
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S544000
Reexamination Certificate
active
06765429
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-92801, filed on Mar. 28, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, particularly to a semiconductor integrated circuit, having a leak current cut-off circuit, which has reduced current dissipation in the waiting condition.
2. Description of the Related Art
In recent years, high speed operation and low power consumption have been requested for the semiconductor integrated circuit to be loaded into mobile electronic apparatuses in order to satisfy the requirement for high speed operation and long-term drive. In order to realize low power consumption, the power supply voltage to be supplied must be lowered. However, when the power supply voltage is lowered, the operation speed is also lowered depending on the power supply voltage. To cover the lowering of operation speed, it is required to design a threshold voltage of each MOS transistor forming the semiconductor integrated circuit to a lower value.
However, when the threshold value of MOS transistor is lowered, a leak current increases in the waiting condition in each MOS transistor and thereby, the low power consumption in the semiconductor integrated circuit may be impeded. As a means for solving such problems, the MT-CMOS (Multi-Threshold-Voltage CMOS) technique as illustrated in
FIG. 1
is known.
FIG. 1
is a schematic diagram illustrating a circuit example of the semiconductor integrated circuit using the conventional MT-CMOS technique. In this Figure,
121
designates an actual power supply line;
122
, a power supply terminal;
123
, a virtual power supply line;
124
-
n
, a logic circuit block;
125
, an internal circuit;
126
, a ground terminal;
127
, a leak current cut-off transistor;
128
, a power control circuit.
In the semiconductor integrated circuit of the conventional art illustrated in
FIG. 1
, in each logic circuit block
124
forming the semiconductor integrated circuit, a plurality of leak current cut-off transistors
127
composed of a high threshold voltage transistor are provided between the power supply terminal
122
connected to the actual power supply line
121
and the virtual power supply line
123
provided within the logic circuit block
124
. The internal circuit
125
is provided between the virtual power supply line
123
and ground terminal
126
. In order to realize high speed circuit operation, the internal circuit
125
is formed of a low threshold voltage transistor having the threshold voltage which is lower than that of the leak current cut-off transistor
127
.
The power control circuit
128
outputs, under the control of a control circuit (CPU or the like, not illustrated), power control signals PCNT
1
~
n
for controlling ON and OFF states of the leak current cut-off transistors
127
provided within each logic circuit block.
When each logic circuit block is activated, corresponding leak current cut-off transistors
127
are turned ON with the power control signals PCNT
1
~
n
and thereby the electrical power is supplied to the internal circuit
125
via the power supply terminal
122
and virtual power supply
123
from the actual power supply line
121
. On the contrary, under the waiting condition of each logic circuit block, the corresponding leak current cut-off transistors
127
are turned OFF with the power control signals PCNT
1
~
n
and thereby, supply of power to the internal circuit
125
is stopped.
Here, the leak current cut-off transistor
127
has the threshold voltage which is higher than that of each MOS transistor forming the internal circuit
125
. Therefore, the leak current cut-off transistor
127
is capable of surely cutting off a current path extended from the actual power supply line
121
via the power supply terminal
122
and virtual power supply line
123
. Accordingly, even when the internal circuit is formed of low threshold voltage transistors, power consumption of the internal circuit can surely be lowered.
FIG. 2
illustrates details of the structure of the leak current cut-off transistor
127
and internal circuit
125
illustrated in FIG.
1
. The logic circuit block is formed in the vertical and horizontal layouts of a plurality of cells. Many cell strings illustrated in
FIG. 2
are arranged in the vertical direction.
Each cell string is structured, for example, as illustrated in FIG.
2
(A), by connecting a plurality of cells (logic gates) which are designed to include both high threshold voltage transistors as the leak current cut-off transistors and low threshold voltage transistors to form an internal circuit, considering the MT-CMOS technique.
On the other hand, when the cells (logic gates) structured only by the low threshold voltage transistors are used in which the MT-CMOS technique is not considered, a cell consisting of a high threshold voltage transistor is designed separately. Then each cell string is structured, as illustrated in FIG.
2
(B), by connecting a plurality of cells consisting of only the high threshold voltage transistors and a plurality of cells consisting of only the low threshold voltage transistors.
In FIGS.
2
(A) and
2
(B), the power control signal PCNTn supplied from the power control circuit is inputted to the gate of the high threshold voltage transistor which acts as the leak current cut-off transistor. Each high threshold voltage transistor is set in the ON and OFF states with the power control signal PCNT-n to control the supply of power to the corresponding logic circuit block.
When, under the condition that the logic circuit blocks in the activated condition exist among a plurality of logic circuit blocks, the other logic circuit blocks in the waiting condition are activated, a problem rises in which a voltage drop of the actual power supply line
121
is temporarily generated in the timing that the corresponding leak current cut-off transistor
127
turns ON. The logic circuit blocks in the activated condition have erroneous operations because of such voltage drop.
FIG. 3
is a diagram for explaining the problems explained above. In regard to
FIG. 3
, an example will be explained in which the logic circuit block
124
-
1
in the waiting condition is activated under the condition that the logic circuit blocks
124
-
2
~
n
are in the activated condition.
As illustrated in
FIG. 3
, the power control circuit changes the corresponding power control signal PCNT
1
to an L (ground potential VSS) level from an H (power supply potential VDD) level in order to activate the logic circuit block
124
-
1
. In response to the level change of the power control signal PCNT
1
, a plurality of leak current cut-off transistors
127
within the logic circuit block
124
-
1
are turned ON simultaneously.
In the moment when the leak current cut-off transistors
127
turn ON, rapid supply of charges to the internal circuit
125
within the logic circuit block
124
-
1
is started and thereby the potential of the virtual power supply line
123
within the logic circuit block
124
-
1
rises rapidly. As a result, a large current flows into the current path from the actual power supply line
121
via the power supply terminal
122
and leak current cut-off transistor
127
.
Accordingly, in this moment, the potential of the actual power supply line
121
temporarily drops to a large extent as illustrated in FIG.
3
. The voltage drop of the actual power supply line
121
is transferred as a power supply noise to the other logic circuit blocks in the activated condition. With the power supply noise, the virtual power supply line of the logic circuit blocks
124
-
2
~
n
in the activated condition also show a large voltage drop to trigger erroneous operations of the logic circuit blocks
124
-
2
~
n.
SUMMARY OF THE INVENTION
The present invention has been proposed considering the problems explained above, and it is there
Arent & Fox PLLC
Zweizig Jeffrey
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