Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2003-05-12
2004-05-04
Tsai, H. Jey (Department: 2812)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S240000, C438S253000
Reexamination Certificate
active
06730525
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
The entire disclosure of Japanese Patent Application No. Hei 9-326851 filed on Nov. 28, 1997 including specification, claims, drawings and summary are incorporated herein by reference in its entirely.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention concerns the formation of electrodes having flat surfaces, and more particularly concerns a method of fabricating capacitors formed by the lamination of a lower electrode, dielectric layer, and upper electrode on a substrate, such as on an insulating film provided in a semiconductor layer, as in the capacitors in ferroelectric memories and DRAMs, etc. The present invention further concerns a method of fabricating capacitors such that the capacitor characteristics are not affected by irregularities in the substrate surface.
2. Description of the Related Art
Such ferroelectric materials as those based on PZT (Pb (Zr, Ti) O
3
) or SBT (SrBi
2
Ta
2
O
9
) are used in the capacitors that configure ferroelectric memories, while high-dielectric materials such as those based on BST ((Ba, Sr) TiO
3
) are used in the capacitors used in DRAMs.
Either Pt or Ir, or an alloy thereof, which is thermally stable and has a lattice constant near that of the ferroelectric material is used for the electrode material in the capacitors noted above. The reason for this is that, in order to crystallize the ferroelectric layer, the lattice constant thereof needs to be matched with the lattice constant of the adjacent ferroelectric material. In addition, the dielectric material, after film formation, is annealed in an oxygen atmosphere at 650 to 850° C. to crystallize it.
Also, noble metal oxides such as IrO
2
, RuO
2
, RhO
2
, and RhO
3
exhibit electrical conductivity, and so are used as electrodes, either laminated with the metal layers noted above, or used by themselves.
These electrode materials are generally made into films by sputtering methods since they are mainly composed of noble metals.
With the capacitor fabrication method described above, however, the following problems are encountered. When a sputtering method is employed, if there are irregularities or foreign matter on the surface of the substrate, irregularities will be formed just like that on the surface of the lower electrode. As diagrammed in
FIG. 4A
, for example, when foreign matter
15
is present on the surface of a substrate
11
, the place where the foreign matter
15
is will mound up when the lower electrode
12
is formed. When a ferroelectric layer
13
is formed thereupon in the same manner, by a sputtering method, an irregularity will also be formed by the foreign matter
15
in the ferroelectric layer
13
, as diagrammed in
FIG. 4A
, and an irregularity will be formed similarly also in the upper electrode
14
on top of that. This irregularity will form a weak point where the film thickness is thin in the ferroelectric layer
13
where a step
21
is, resulting in low voltage resistance and a danger of shorting out between the two electrodes.
The same sort of problem arises when using a vacuum vapor deposition or CVD method. And when the ferroelectric layer
13
is formed using a sol-gel method, problems such as those noted below arise.
As diagrammed in
FIG. 4B
, the surface of the dielectric layer
13
is flattened, and the upper electrode
14
is also formed flat. However, at the place where the lower electrode
12
mounds up due to foreign matter
15
on the substrate
11
, the film thickness of the ferroelectric layer
13
becomes very thin, forming a weak point, and leading to the same problems as noted earlier.
There are also surface irregularities that are caused not by foreign matter but by crystal grain. As diagrammed in
FIG. 5
, for example, when a capacitor is formed on something like a polysilicon film
16
, the dielectric layer film thickness becomes locally thin due to irregularities in the surface thereof, just as when there is foreign matter, resulting in crystallinity degradation and flaws.
Also, when forming plugs of polysilicon or tungsten (W) in contact holes provided in SiO
2
films and the like, there are instances where steps form between the surfaces of the SiO
2
and the plug. The same thing is true in cases of such steps.
SUMMARY OF THE INVENTION
An object of the present invention is to resolve the problems noted in the foregoing, providing electrodes the upper surfaces of which are flat even when there are irregularities in the lower surface of the electrode. More specifically, this object is to flatten the surface of the lower electrode in the ferroelectric layer. Another object of the present invention is to make the film thickness uniform in the ferroelectric layer formed on the electrode, even when there are irregularities on the lower surface of the electrode. Another object of the present invention is to provide capacitors that exhibit good capacity characteristics and voltage resistance, and wherewith improved production yield can be realized.
The electrode formation method in the present invention is a method of forming electrodes wherein electrodes made from materials containing a noble metal are formed on a substrate, wherein also the noble metal is converted to a compound that can be dissolved in a solvent, and formed into a liquefied coating agent that is coated onto the substrate, after which the liquid noble metal is solidified to from the lower electrode.
The capacitor fabrication method based on the present invention is one wherein a lower electrode made from material containing a noble metal is formed on a substrate, a dielectric layer is formed on the lower electrode, and an upper electrode is formed on the dielectric layer, characterized further in that the lower electrode is formed so that the surface thereof is flattened, by applying a coating agent wherein the electrode material is liquefied, and in that the dielectric layer is provided on the lower electrode.
The capacitor fabrication method in the present invention is a method wherein a lower electrode made from material containing a noble metal is formed on a substrate, a dielectric layer is formed on the lower electrode, and an upper electrode is formed on the dielectric layer, further characterized in that the lower electrode is formed so that the surface thereof is flattened by applying an electrode material coating agent, and in that the dielectric layer is provided on the lower electrode.
By noble metal here is meant a thermally and chemically stable metal exhibiting outstanding electrical conductivity, such as Au, Pt, Ir Os, Ag, Pd, Rh, Ru, or Re.
It is particularly effective to form the dielectric layer from a ferroelectric material or a high-dielectric material.
More particularly, an organic compound or halide of the noble metal is dissolved in an organic solvent to form a coating agent, this coating agent is applied to the substrate, and the organic material or halogen is then evaporated. By so doing it is possible to form a lower electrode the surface whereof is flattened.
When the lower electrode is formed from an electrically conductive material made into a laminated structure, if at least one of the layers in that laminated structure is flattened by the application of the coating agent, the surface of the lower electrode will be flattened.
When evaporating the organic material or halogen, it is possible also to form an electrically conductive oxide consisting of the oxide of the noble metal, whereupon a lower electrode consisting of a metal material can be formed by reducing the oxide of the noble metal.
The characteristics of the present invention, together with other objects, applications, and benefits thereof, etc., should become more evident upon perusal of the embodiments and drawings.
REFERENCES:
patent: 5100702 (1992-03-01), Maeda et al.
patent: 5130172 (1992-07-01), Hicks et al.
patent: 5665643 (1997-09-01), Shin
patent: 5728626 (1998-03-01), Allman et al.
patent: 5763020 (1998-06-01), Yang
patent: 5783716 (1998-07-01), Baum et al.
patent: 5897912 (1999-04-01), Shaikh
patent: 6150183 (200
Merchant & Gould P.C.
Rohm & Co., Ltd.
Tsai H. Jey
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