Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Unwanted signal suppression
Reexamination Certificate
2001-09-26
2004-01-20
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Unwanted signal suppression
C327S552000, C708S300000
Reexamination Certificate
active
06680644
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to electronic systems and applications utilizing phase-locked loops, and more specifically to a method and system to filter a randomly jittered clock.
2. Description of the Related Art
Phase-locked loops are widely known in the art of electronics and are utilized in many applications of electronics to control the frequency and phase of a signal. One application of phase-locked loops is the recovery of a transmission clock from a data communications medium. When a reference clock for a phase-locked loop is randomly jittered, successive cycles of the clock exhibit a non-linear deviation in phase. Random jitter in a reference clock causes the phase-locked loop to perform poorly, which in turn, leads to inadequate performance of a system in which the phase-locked loop is providing a main system clock.
Solutions to prevent jitter created by the reference clock to the phase-locked loop have been inadequate due to high cost and difficulty in implementation. A first method of removing jitter known to the art involves the use of a digital phase-locked loop followed by an analog phase-locked loop. Another method of removing jitter involves the use of a robust analog phase-locked loop and a voltage controlled crystal oscillator along with a sophisticated active low-pass filter. While each of these methods may reduce clock jitter, each is accompanied by large manufacturing costs.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a novel system and method of filtering a clock reference which may be accompanied by random jitter. In a first aspect of the present invention, a filter of the present invention may block extreme deviations of the reference clock. In an exemplary embodiment of the present invention, the filter of the present invention may check that a reference clock is received within a pre-defined window. When a clock reference is received within the window, it may pass and be utilized in a system application. A reference clock may be ignored when the reference clock is not received within the window. When a reference clock is not received within the window, an interpolated clock representing an ideal received clock may be utilized as a reference. In another aspect of the present invention, the filter of the present invention may reject high-frequency jitter while allowing low-frequency jitter to pass. In an exemplary embodiment of the present invention, the filter of the present invention may be capable of automatically centering itself to allow low-frequency jitter to be tracked while rejecting the high-frequency jitter.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.
REFERENCES:
patent: 4791386 (1988-12-01), Shiga
patent: 6424687 (2002-07-01), Tian et al.
patent: 11186906 (1999-07-01), None
Le Dinh T.
Siemens Information & Communication Networks, Inc.
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